6.10.2. ATB 1:1 bridge synthesis

You must use the ATB 1:1 bridge to achieve timing closure when the CoreSight components are spread out across an ASIC. This might happen if, for example, layout constraints require that a trace source is placed close to the processor or bus that it is tracing.

The ATB 1:1 bridge consists of a set of registers across the data interface and the control signals that are emitted from trace sources. This bridge has two ATB interfaces, an input and an output. Both interfaces exist in the same clock domain.

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