CoreSight Technology System Design Guide: 5.2.1. Differences between on-chip and off-chip storage

5.2.1. Differences between on-chip and off-chip storage

To decide when to implement an ETB or ETR for on-chip storage, or a TPIU for off-chip storage in a TPA, you must consider the following:

You can capture much more trace in a TPA than in an ETB or ETR. This has the following advantages:
- You require fewer trace runs to identify the cause of a bug. The cause of the bug is less likely to have been overwritten.
- The trace requires less filtering. You can increase the effective size of the buffer considerably by using filtering resources to trace only important events, for example when the processor executes a particular function. This can lead to the loss of important trace because the system accidentally filters it out. Filtering resources also take time to set up, slowing down the development process.
- You can perform more accurate profiling. Code profiling requires trace over a long time to be accurate.
An ETB and ETR can capture trace at a much higher speed. This enables the system to capture far more detailed trace over short periods. For example, a very high speed system might not be able to dedicate enough pins to capture full data trace from a processor off-chip, but might be able to capture the same trace on-chip in an ETB or ETR.
An ETB or ETR do not require any trace pins. Your system might require a large number of pins if:
- It must trace a large amount of data simultaneously. For example, if you want to provide full data trace of several cores at the same time, your system requires a large number of pins.
- The trace port speed is much less than the speed of the components being traced. For example, in a system with a 250MHz trace port clock, four times as many pins are required to trace a processor running at 1GHz than are required to trace the same processor running at 250MHz.
On-chip trace storage requires considerable silicon area. The size of the on-chip RAM can be substantial, depending on the maximum size of trace window that you have to support You can offset this with the reduction in I/O pads that also use silicon area or by reusing the memory for run-time usage when trace is not required.

Systems with an ETB and a TPIU

Sometimes it is advantageous to implement a TPIU with its Trace Port, and an on-chip buffer such as an ETB, in the same chip. See Figure 5.1. Usually the Trace Port in such devices is only capable of a small amount of trace, for example, it might only have sufficient bandwidth for instruction trace. This permits you to use the trace in different ways:

Use the on-chip buffer when you require full trace over a short period. This is most useful when debugging the behavior of a well-defined section of software, when you can use filtering and the time between an error in the code and the detection of the bug by the trigger condition is small.
Use the TPIU and TPA when you require trace over a long period. For example, when you cannot use filtering, or the time between an error in the code and the detection of the bug by the trigger condition is large.
Use the TPIU and TPA when you derive profiling information from the trace. This requires a large amount of information and is usually concerned only with instruction trace.

In systems where the same ATB feeds both the on-chip trace sink and TPIU, it is not recommended that you enable both devices at the same time. If you do this, the device with the higher potential bandwidth receives trace at the same rate as the slower one. For example, a 32-bit ETB can only have a quarter of its maximum bandwidth as a similarly clocked TPIU if the TPIU is configured to only use 8-bits of the Trace Port and is operating on the same trace data stream. This is because a replicator stalls its input if either output stalls.

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