6.6.1. CoreSight system clock design

Requirements of the clock implementation are:

PCLKDBG greater than ATCLK is unsupported.

It is expected that system-level access through the AHB-AP, running from HCLK and software access to the Debug APB through the DAP, running from PCLKSYS, are the same AMBA interconnect clock. If this is the case, HCLK and PCLKSYS are equivalent.

In summary:

PCLKDBG is equivalent to DAPCLK.

PCLKDBG, DAPCLK, and ATCLK must be synchronous.

PCLKDBG is less than or equal to ATCLK.

HCLK and PCLKSYS, in a typical system are equivalent.

For system implementations where PCLKDBG is less than ATCLK, it is recommended that CoreSight components requiring both ATCLK and PCLKDBG:

For any clock domain where a clock enable is not required, connect the corresponding clock enable port HIGH.

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