4.2.2. DAP access

The purpose of the DAP is to create a bridge between different bus structures and external tools. At a basic level, it has one input controlling interface, the Debug Port (DP), and several output masters, the APs.

The DAP can provide a bridge to:

The structure of the DAP provides a single flexible and scalable platform for access to locations throughout an entire SoC. The internal design of the DAP gives each AP independence from the controlling DP permitting connections across different clock and power domains.

The DAP supplied with the Design Kit permits an independent AHB power domain and can manage transactions from the System APB in a different power domain. However, the main DAP and the Debug APB must use the same clock.

Individual Access and Debug Ports within the DAP provide different features that might not be present in existing solutions:


This AP gives direct access to an AHB bus, or AXI bus through a bridge, and does not require a processor to stop or scan instructions though the processor. The AHB-AP only performs single transactions over AHB so that invasiveness is kept low. To decrease invasiveness more, it is recommended that the bus arbiter selects the AHB-AP as a low priority master.

The AHB-AP connects directly to the bus, therefore there is no overhead for transfers because there is no requirement to translate reads and writes into Op Codes for the processor.


The AHB-AP bypasses the processor to access the memory subsystem and views the physical bus addresses. This is not the same for the processor that views the virtual addresses.


This component maintains the existing JTAG based debugging of cores. With independent JTAG chains, it is possible to have a JTAG chain attached to a core that might power-down, for example as part of an IEM domain, without affecting the JTAG access to other chains.


The DAP permits the APB-AP to be a dedicated channel for control of and access to debug and trace components. This use of an AP for debug components ensures that there is no invasiveness onto the system bus.

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