Appendix A. Revisions

This appendix describes the technical changes between released issues of this book.

Table A.1. Differences between issue B and issue C

Replaced ‘The CoreSight Design Kit’ with ‘CoreSight Technology’Throughout bookAll revisions
Replaced JTAG-Port with SWJ-Port in Figure 1.1Figure 1.1All revisions
Updated the Cross Triggering section Cross TriggeringAll revisions
Added AMBA Advanced eXtensible Interface (AXI) description to CoreSight components sectionCoreSight componentsAll revisions
Updated Trace sources section Trace sourcesAll revisions
Updated Trace links sectionTrace linksAll revisions
Updated Trace sinks sectionTrace sinksAll revisions
Updated External debug hardware and software section External debug hardware and softwareAll revisions
Updated About CoreSight technology and ETM architectures features section for CoreSight technology componentsAbout CoreSight Technology and ETM architectures featuresAll revisions
Updated Identification Register value for SW-DP, and SWJ-DPTable 3.1All revisions
Added STM to the Trace source HTM and ITM features tableTable 3.4All revisions
Added Embedded Trace FIFO (ETF) to Link component featuresTable 3.6All revisions
Added ETB to Sink component features, part 1Table 3.7All revisions
Added ETR to Sink component features, part 2Table 3.8All revisions
Added Cortex - A9 and Cortex - A5 to Debug components, part 2Table 3.10All revisions
Added PFTv1 description to Architectural Features of ARM trace sources sectionArchitectural features of ARM trace sourcesAll revisions
Added CS PTM-A9 and CS ETM-A5 to ARM trace source component features, part 2Table 3.12All revisions
Added new section for access to debug componentsAccess to debug components All revisions
Added STM connection information in Table 4.3Table 4.3All revisions
Added TMC connection information in Table 4.4Table 4.4All revisions
Added new section for Mixing JTAG devices with SWJ-DPMixing JTAG devices with SWJ-DPAll revisions
Updated the Designing your trace system section, also added a new section, Using additional buffers in trace systemsDesigning your trace systemAll revisions
Replaced JTAG power and JTAG interface with SWJ power and SWJ interface respectivelyPower domains and system design All revisions
Updated DAP sectionDebug Access Port (DAP)All revisions
Updated Power up request and acknowledge signal connections tableTable 6.1All revisions
Added CSRTCK, return test clock to the CoreSight Technology clocks tableTable 6.2All revisions
Updated CoreSight system clock design section for descriptionCoreSight system clock design All revisions
Added HTMHRESETn and nSRSTOUT, reset signals to CoreSight Technology reset signals tableTable 6.3All revisions
Updated the nPOTRST description in Connection of CSDK resets sectionConnection of CSDK resetsAll revisions
Replaced JTAG-DP with SWJ-DPTools controlled debug resetAll revisions
Replaced JTAG interface with SWJ interfaceDAP placementAll revisions
Updated the description in TPIU TRACECLK generation sectionTPIU TRACECLK generationAll revisions

Table A.2. Differences between issue C and issue D

Updated the Figure 6.8 for Clk1 and Clk2 key statementFigure 6.8All revisions

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