1.1. About CoreSight systems

CoreSight systems provide all the infrastructure you require to debug, monitor, and optimize the performance of a complete System on Chip (SoC) design.

Historically, the following methods of debugging an ARM processor based SoC exist:

CoreSight Technology addresses the requirement for a multi-core debug and trace solution with high bandwidth for whole systems beyond the core, including trace and monitor of the system bus.

CoreSight Technology provides:

CoreSight Technology addresses a number of trends in SoC design that increase the debug challenge:

Frequency increases and trace generation

Systems are tracing more information per second and must transfer this out of the SoC. Pin interface frequencies are not rising as fast as on-chip frequencies.

Design Complexity

The interactions between cores in SoCs are crucial to understanding system behavior. System logic is sufficiently decoupled from core execution to require direct visibility. For example, a system cannot determine from inside a processor with cache, the amount of time a peripheral takes to respond to a memory request.

Clock and power domain implementations are complicated. The clock frequencies can change and any part of the system can enter a low-power mode at any time. Conventional JTAG-based systems must disable all power saving features to provide debug, but in many situations this is not acceptable.

Pin count

Pin count is crucial. Chip package restrictions do not permit a separate trace port for each core in a chip and static switching between trace ports prevents debug of complex interactions.

SoC designs must be flexible to provide the correct number of pins to achieve the required trace capture capabilities. It is not acceptable to double the number of pins because the frequency is 10% too high, or because the data bandwidth is 5% too high.

Performance optimization

Products must reach their performance targets. To make the most of high performance cores in SoC designs, it is essential to profile processor and bus activity to optimize performance.

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