3.2.3. Link features

Table 3.5 and Table 3.6 shows the link component features.

Table 3.5. Link component features, part 1

Component nameATB 1:1 Synchronous BridgeTrace Funnel Replicator
CoreSight CompliantYesYesYes
DescriptionATB link to enable timing closure when intra-chip propagation delays might affect timingTrace link that enable multiplexing of up to eight trace streams into a single streamComponent to enable dual sampling of trace data on two independent ATB slave components
FeaturesFully registered interfacesStatic priority arbitration, minimum hold time-
ATB input1 x 32-bit8 x 32-bit1 x 32-bit
ATB Output1 x 32-bit1 x 32-bit2 x 32-bit
ATB Clocking requirementsInput and output the sameInput and output the sameInput and output the same
Memory FootprintNone4KBNone
Designer ID-ARM (0x43B)-
Part number-0x908-
Device ID-0x0A0-
Device type 0x11 
Lock Access Register Bypassable 
Claim tags-4 bits-
Topology detectionCompatibleYesCompatible
Integration registersCompatibleYesCompatible

Table 3.6. Link component features, part 2

Component nameAsynchronous bridgeUpsizerEmbedded Trace FIFO (ETF)[a]
CoreSight CompliantYesYesYes
DescriptionATB link to enable crossing of independent clock and/or power domains.Component to adapt 8-bit ATB outputs of narrow trace sources to 32-bit ATB as used in the majority of CoreSight components.Large ATB FIFO using a private SDRAM for buffering of trace data.
FeaturesBuffer to cross clock domains efficiently.-Buffer large quantities of trace data to allow averaging of bandwidth over larger windows of time. Can also operate as a traditional ETB, circular buffer based trace sink.
ATB input1x [8 to 128-bit]1x 8 bit1x [32-bit to 128-bit]
ATB Output1x (same width as input)1 x 32 bit1x (same width as input)
ATB Clocking requirementsInput and output fully asynchronousInput and output the sameInput and output the same
Memory FootprintNoneNone4KB
Designer ID--ARM (0x43B)
Part number--0x961
Device ID--Configurable
Device type--0x32
Lock Access Register--Bypassable
Claim tags--4-bits
Topology detectionCompatibleCompatibleYes
Integration registersCompatibleNoYes

[a] The ETF is a configuration option of the Trace Memory Controller (TMC)

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