2.2.5. Trace sinks

Sinks are the endpoints for trace data on the SoC. CoreSight provides sinks that the following sections describe:

Trace Port Interface Unit (TPIU)

The TPIU is an ATB slave that drains trace data off the chip. It acts as a bridge between the on-chip trace data and a data stream that is captured by a Trace Port Analyzer (TPA). The formatter within the TPIU combines the source data and IDs into a single data stream, to enable serialization of data, inserting trigger packets on trigger detection. You can bypass formatting if your system only traces a single source, and in this situation, no IDs are embedded. The TPIU supports off-chip port sizes from 2 to 34 pins. The off-chip trace port can operate asynchronously to the incoming trace data. Figure 2.4 shows a block diagram of the TPIU.

Figure 2.4. TPIU block diagram

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The TPIU has the following ports:

  • a Debug APB programming interface

  • an ATB slave port for receiving trace data from a source or link

  • an asynchronous Trace Port (TP) at the pins of the device for connection to a TPA

  • trigger ports for connection to a CTI.

For more information, see the CoreSight Technical Reference Manual.

Embedded Trace Buffer (ETB)

The Embedded Trace Buffer (ETB) is an ATB slave and provides on-chip storage of trace data using a configurable sized RAM. The ETB stores data as follows:

  • The ATB bus receives Trace Data.

  • The Formatter in the ETB combines the source data and IDs into a single data stream. The Formatter operates in an identical manner to the Formatter in the TPIU.

  • The ETB stores the data in RAM.

You can bypass formatting if your system only traces a single source, and so reduce the amount of data stored in RAM. The ETB accesses RAM using read and write pointers to permit memory access through the APB interface. Figure 2.5 shows a block diagram of the ETB.

Figure 2.5. ETB block diagram

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The ETB has the following ports:

  • a Debug APB programming interface

  • an ATB slave port for trace data for a source or link

  • trigger ports for connection to a CTI

  • a memory Built In Self Test (BIST) interface.

Serial Wire Output

Serial Wire Output (SWO) is a trace sink similar to the TPIU. It can only trace one source, the ITM. It outputs the data stream off-chip through a single-pin interface. You can select between the following operating modes for the single pin output:

  • Manchester encoded stream

  • NRZ-based UART byte structure, start bit, data bits, stop bit.

The SWO has an 8-bit ATB slave interface that you can connect to the CoreSight ITM. The SWO and the ATB interface are collectively called the Serial Wire Viewer (SWV).

Trace Port Interface Unit Lite

The Trace Port Interface Unit Lite (TPIU-Lite) is a reduced feature, low gate count version of the TPIU. The following differences apply:

  • A synchronous trace port that operates at ATCLK speed.

  • Single trace source only. There is no formatter.

  • 2-bit, 4-bit, 8-bit, 16-bit, and 32-bit trace port widths.

  • No pattern generator.

Embedded Trace Router (ETR)

The ETR is a trace sink that redirects the trace stream onto AXI. It can utilize a single contiguous region or a scattered allocation of blocks for a circular buffer. Reading of the AXI based trace buffer can either be done directly over AXI from a normal bus master, or through the ETR as if it were an ETB. You can also program it to stream trace data to a single address location for use with high-speed links.The ETR is a configuration option of the TMC.

Enhanced ETB

An enhanced ETB is available as a configuration option of the TMC. This configuration is similar to the Classic ETB with extra features such as being able to FIFO trace data to the Debug APB interface and more memory size options.

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