3.2.5. Debug features

Table 3.9 and Table 3.10 shows the debug component features.

Table 3.9. Debug component features, part 1

Component nameDAP-ROM[a]CTICTM
CoreSight compliantYesYesYes
DescriptionTable for pointers to various debug and trace components present on the same memory structure.Interface to enable the cross connection of any attached debuggers to and from other trigger stimulus ports.Channel link to enable more than two CTIs to link together and share trigger information.
FeaturesBegins in a blank format and must be updated by the system creator to reflect the system implementation with allocation for 32 components.Eight trigger inputs and eight outputs with extra levels of multiplexing possible, selectable handshaking and synchronizers.Four-way interconnect, connects to CTIs or other CTMs to link up larger numbers of CTIs. Selectable handshaking and synchronizers on channel interfaces.
Non-programming interfacesNone

8x Trigger inputs

8x Trigger Outputs

1x Channel Interface

4x Channel Interface
Memory Footprint4KB4KBNone
Designer IDImplementation definedARM (0x43B)-
Part numberImplementation defined0x906-
Device IDNon-applicable0x40800-
Dev TypeNon-applicable0x14-
Lock Access RegisterNoBypassable-
Claim TagsNone8-bits-
Topology detectionNon-applicableYesCompatible
Integration registersNon-applicableYesCompatible

[a] The DAP-ROM is supplied as part of the DAP and DAP-Lite.


Table 3.10. Debug component features, part 2

Component nameCTI-A8Cortex-A9Cortex-A8Cortex-A5Cortex-R4
CoreSight compliantYesYesYesYesYes
DescriptionInterface to enable the debug logic, ETM and PMU to interact with each other and with other CoreSight components.Debug Interface to the Cortex-A9 processor.Debug Interface to the Cortex-A8 processor.Debug Interface to the Cortex-A5 processor.Debug Interface to the Cortex-R4 processor.
FeaturesImplements a configured set of seven trigger inputs and nine trigger outputs of which some are externally defined.The processor debug unit provides a set of control registers to enable stopping of programexecution, examining and altering processor state and restarting the processor core.The processor debug unit provides a set of control registers to enable stopping of program execution, examining and altering processor state and restarting the processor core.The processor debug unit provides a set of control registers to enable stopping of programexecution, examining and altering processor state and restarting the processor core.The processor debug unit provides a set of control registers to enable stopping of program execution, examining and altering processor state and restarting the processor core.
Non-programming interfaces

9x Trigger inputs

9x Trigger Outputs

1x Channel Interface

----
Memory Footprint4KB4KB4KB4KB4KB
Designer IDARM (0x43B)ARM (0x43B)ARM (0x43B)ARM (0x43B)ARM (0x43B)
Part number0x9220xC090xC080xC050xC14
Device ID0x409060x00x00x00x0
Dev Type0x140x150x150x150x15
Lock Access RegisterBypassableBypassableBypassableBypassableBypassable
Claim TagsNone8-bits8-bits8-bits8-bits
Topology detectionYesYesYesYesYes
Integration registersYesYesYesYesYes

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