3.3. Architectural features of ARM trace sources

The ETM and PTM are trace sources that monitor ARM processors. Each ETM and PTM are associated with certain processor lines, and each ETM and PTM version conforms to certain ETM and PTM architectures. The architecture consists of a generic programmers model and a trace protocol. The ETM programmers model is consistent for the main revisions of the architecture but the protocol has developed.


The first ETM Architecture. Used on ETM9 and ETM7 devices. Pipeline execution of instructions is represented within a 3-bit bus on a cycle-by-cycle basis of the activity of the core, PIPESTAT, and data trace appears on a separate, independent bus, TRACEPKT.


An extension of ETMv1 with more structured information appearing on the secondary information pipeline, TRACEPKT, with the introduction of P-Headers, packet header, and an increase of the PIPESTAT bus to 4-bits to provide more optimal indication of processor execution.


Major revision to previous ETM protocols. All information, data transfers, and instruction execution, is based on byte-size packets with no pipeline status. Data suppression enhances FIFO usage and reduces overflow regularity. The byte protocol and the removal of PIPESTAT make it possible to implement asynchronous trace outputs and support CoreSight.


A new protocol designed to only offer program flow trace, where only branches and exceptions are traced using minimal trace bandwidth. The protocol is byte- based, similar to ETMv3. The PFT architecture is fully CoreSight-complaint.

For more information about the ETM and the various architectural differences, see the ETM Architecture Specification.

For more information on the PTM architecture, see the PTM Architecture Specification.

Table 3.11 and Table 3.12 list the features of the ETMs.

Table 3.11. ARM trace source component features, part 1

FeatureETM9, medium plusETM11RVCoreSight ETM9CoreSight ETM11
Architecture versionETMv1.0-v1.3ETMv3.1ETMv3.2ETMv3.2
Address comparator pairs4444
Data comparators2222
Context ID comparators-111
Start/stop blockYesYesYesYes
EmbeddedICE comparators2020
External inputs4444
External outputs1222
Extended external inputs-20020
Extended external input selectors0202
ASIC Control Register bits8888
Data suppression-YesYesYes
Software access to registers-CoprocessorMemoryMemory
Readable registers-YesYesYes
Fifo size45696072
Fetch comparisonsYesNoNoNo

[a] Yes = supported.

Table 3.12. ARM trace source component features, part 2

Architecture versionPFTv1.0ETMv3.3ETMv3.5ETMv3.3ETMv3.4
Address comparator pairs44440
Data comparators02220
Context ID comparators11110
Start/stop blockYesYesYesYesYes
EmbeddedICE comparator inputs00004
External inputs44442
External outputs22220
Extended external inputs524930470
Extended external input selectors22220
ASIC Control Register bits88880
Data suppressionN/AYesYesYesNo
Software access to registersMemory MemoryMemoryMemoryMemory
Readable registersYesYesYesYesYes

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