3.2.1. DAP features

The DAP is the bridge for access to the Debug APB and system busses. Table 3.1 shows the DAP component features for Debug Ports.

Table 3.1. DAP component features for Debug Ports

Component nameJTAG-DPSW-DPSWJ-DP
ADIv5 Architecture ComplianceJTAG-DPSW-DPJTAG-DP and SW-DP
DescriptionExternally visible TAP that links to various on chip master interfacesLow pin count, clock plus bidirectional data, alternative to a conventional JTAG interfaceCombined TAP and Serial Wire interface, effectively JTAG-DP and SW-DP, with a switching sequence to translate between pin modes
Identification Register, excludes revision value0xBA004770xBA01477

0xBA02477 Serial Wire

0xBA00477 JTAG

Manufacturer/designerARM (0x43B)ARM (0x43B)ARM (0x43B)
Part Number/AP Identification0xBA000xBA01

0xBA01 Serial Wire

0xBA02 Serial Wire with Multidrop support


Input interfaceJTAGSerial WireShared JTAG and Serial Wire
Output interfaceDAP internal busDAP internal busDAP internal bus
Authentication supportNoNoNo
Power control supportYesYesYes
Abort mechanismInitiatorInitiatorInitiator

Table 3.2 shows the CoreSight components for Access Ports.

Table 3.2. DAP component features for Access Ports

ADIv5 Architecture ComplianceMem-APMem-APJTAG-APMem-AP
DescriptionDAP interface to an AHB systemDAP interface to the Debug APBDAP interface to on-chip TAP controllersDAP Interface to Cortex-M3 system including debug components
Identification Register, excludes revision value0x47700010x47700020x47700100x4770011
Manufacturer/designerARM (0x43B)ARM (0x43B)ARM (0x43B)ARM (0x43B)
Part Number/AP Identification0x01, AHB Bus0x02, APB Bus0x10, JTAG connection0x11, AHB Bus
Input interfaceDAP internal busDAP internal busDAP internal busDAP internal bus
Output interfaceAHB-LiteAPBMultiple JTAGCortex-M3 internal AHB
Authentication supportYesYesYesYes
Power control supportYesNoYesAsynchronous check only
Abort mechanismSystem transfer maintained. DAP internal bus released.System transfer maintained. DAP internal bus released.Aborts any JTAG transactions in progress. DAP internal bus released. JTAG-AP is returned to its reset condition. FIFOs are cleared and all registers are returned to their reset values.System transfer cancelled through functional reset of the bus matrix, permitting access to NVIC and debug components.

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