2.2.2. Control and access components

Control and access components configure, provide access to, and control debug logic and the generation of trace. They do not generate trace, or process the trace data. The CoreSight control and access components are:

Debug Access Port

The DAP enables debug access to the complete SoC through system master ports. Figure 2.2 shows the structure of the DAP.

Figure 2.2. Structure of the CoreSight DAP component

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Access to the CoreSight Debug APB is enabled through the APB Access Port (APB-AP) and APB Multiplexer (APB-Mux), and system access is provided through the AHB-AP and JTAG Access Port (JTAG-AP). The DAP has the following interface blocks:

  • External Serial Wire or JTAG access using the Serial Wire/JTAG Debug Port (SWJ-DP).

  • Internal system access using:

    • AHB-AP

    • APB-AP

    • JTAG-AP

    • AHB-AP for Cortex-M3, if present.

  • An APB-Mux enables system access to CoreSight components connected to the Debug APB.

  • The ROM table provides a list of memory locations of CoreSight components connected to the Debug APB. This is visible from both tools and system access and you must configure it during system implementation.

External read/write access to the internal interface is provided by the SWJ-DP. The SWJ-DP provides both a standard interface and an ARM Serial Wire Debug interface for debug access to an SoC through the DAP. It interfaces to the DAP internal bus.

Internal access to on-chip busses and other interfaces is provided by the Access Ports (APs). The APs are as follows:

  • the AHB-AP that provides an AHB-Lite master for access to a system AHB bus

  • the APB-AP that provides an AMBA 3 APB master for access to the Debug APB that configures all CoreSight components

  • the JTAG-AP that provides JTAG access to on-chip components and operates as a JTAG master port to drive JTAG chains throughout the SoC.

For more information, see the CoreSight Design Kit Technical Reference Manual.

Embedded Cross Trigger

The ECT is a modular component that supports the interaction and synchronization of multiple triggering events within a SoC.

The ECT consists of the following types of module:

  • A CTI. The CTI provides the interface between a component or subsystem and the Cross Trigger Matrix (CTM). The system requires a CTI for each subsystem that supports cross triggering.

  • A CTM. The CTM combines the trigger requests generated from CTIs and broadcasts them to all CTIs as channel triggers. This enables subsystems to interact, cross trigger, with one another. You can connect CTMs together to increase the number of CTIs.

For more information, see the CoreSight Design Kit Technical Reference Manual.

Copyright © 2004, 2007, 2010 ARM Limited. All rights reserved.ARM DGI 0012D