3.2.2. Source features

Table 3.3 shows the trace source ETM component features.

Table 3.3. Trace source component features

Component nameETM9CSETM11CSETM-A8ETM-R4ETM-M3
CoreSight compliantYesYesYesYesYes
DescriptionTrace source for instruction and data trace of the synthesizable ARM9 family of processorsTrace source for instruction and data trace of the ARM11 family of processorsTrace source for instruction and data address trace of the Cortex-A8 processorTrace source for instruction and data trace of the Cortex-R4 and R4F processorsTrace source for instruction only trace of the Cortex-M3 processor
FeaturesInstruction only trace, data only trace, instruction and data trace, data suppressionInstruction only trace, data only trace, instruction and data trace, data suppressionInstruction only trace, data address only trace, instruction and data address trace, data suppressionInstruction only trace, data only trace, instruction and data trace, data suppressionInstruction only trace
ATB output32 bit32 bit32 bit32 bit8 bit
Architecture referenceETMv3.2ETMv3.2ETMv3.3ETMv3.3ETMv3.4
Stimulus inputARM9ARM11Cortex-A8Cortex-R4Cortex-M3
Memory footprint4KB4KB4KB4KB4KB
Designer IDARM (0x43B)ARM (0x43B)ARM (0x43B)ARM (0x43B)ARM (0x43B)
Part number0x9100x9200x9210x9300x924
Device ID0x00x00x00x00x0
Device type0x130x130x130x130x13
Lock Access RegisterBypassableBypassableBypassableBypassableYes
Claim tagseight bitseight bitseight bitseight bitseight bits
Topology detectionYesYesYesYesYes
Integration registersYesYesYesYesNo

Table 3.4 shows the trace source HTM and ITM features.

Table 3.4. Trace source HTM and ITM features

Component nameHTMITMCM3-ITMSTM
CoreSight compliantYesYesNoYes
DescriptionTrace source for AHB based activity. Behaves as a passive bus watcher.Software generated trace source designed for printf style debugging requiring memory accesses to generate stimulus.Software generated trace source for within the Cortex-M3 platform. Also includes the ability to trace data values through the Debug Watch Trace unit.Software generated trace source designed for printf style debugging requiring memory accesses to generate stimulus. It can also generate trace based on activity of a set of hardware stimulus ports.
FeaturesAddress trace, data trace, address and data trace, data suppression.32 virtual stimulus registers, trigger generation on stimulus writes, maskable trace generation based on authentication level.32 virtual stimulus registers, maskable trace generation based on transaction type.64K virtual stimulus registers, trigger generation on stimulus writes, global time-stamping on stimulus writes, both lossy and guaranteed channels on stimulus generation, maskable trace generation based on Authentication level, 32 hardware based stimulus events.
ATB output32-bit8-bit8-bit32-bit
Architecture referenceNoneNoneNoneSTPv2, protocol
Stimulus input32-bit or 64-bit AHBAPBAHBAXI
Memory footprint4KB4KB4KB excluding DWT control4KB excluding AXI stimulus ports
Designer IDARM (0x43B)ARM (0x43B)ARM (0x43B)ARM (0x43B)
Part number0x9170x9130x0010x962
Device ID0x00x020Non-applicable0x10000
Device type0x430x43Non-applicable0x43
Lock Access RegisterBypassableBypassableYesBypassable
Claim tags4-bit8-bitNone4-bit
Topology detectionYesYesYesYes
Integration registersYesYesNoYes

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