3.2.4. Sink features

Table 3.7 and Table 3.8 shows the sink component features.

Table 3.7. Sink component features, part 1

Component nameETB11TPIUCS ETBETB[a]
CoreSight compliantNoYesYesYes
DescriptionOnchip trace capture device for capture of non-CoreSight legacy ETMs.Parallel trace port for interfacing on-chip trace to off-chip capture devices.Provides on-chip storage of trace dataProvides on-chip storage of trace data in a local SRAM.
Features-Includes pattern generation for thorough analysis of pin timing.-Includes programmable mode to use the SRAM as a FIFO when taking data over the Debug APB interface.
ATB inputNon-applicable32 bit32 bit32-bits to 128-bits
Parallel Trace PortNo

1-32 data pins

1 clock pin

1 optional control pin

Serial Wire OutputNoNoNoNo
Data Storage1KB to 1MBNone1 KB to 1 MB1KB to 4GB
Memory Footprint4KB + Memory size4KB4KB4KB
Designer IDNon-applicableARM (0x43B)ARM (0x43B)ARM (0x43B)
Part numberNon-applicable0x9120x9070x961
Device IDNon-applicable0x0A00x000Configurable
Dev TypeNon-applicable0x110x210x21
Lock Access RegisterNoBypassableBypassableBypassable
Claim TagsNone4 bits4 bits4-bits
Topology detectionNoYesYesYes
Integration registersNoYesYesYes

[a] The ETB is a configuration option of the Trace Memory Controller (TMC).

Table 3.8. Sink component features, part 2

Component nameTPIU-LiteSWOCM3 TPIUEmbedded Trace Router (ETR)[a]
CoreSight compliantYesYesYesYes
DescriptionLow gate count parallel trace interface between on-chip trace and off-chip capture devices.Serial Wire output for Instrumentation Trace Macrocell trace to off-chip capture devices.Cortex-M3 specific, parallel and serial trace interface to off-chip trace capture devices.Provides on-chip storage of trace data in the system through an AXI interface.
Features--Includes trace funnel

Contains the following modes of using the system memory:

  • basic circular buffer, single contiguous block of memory

  • circular buffer using scatter-gather, list of arbitrary blocks of memory

  • single location for streaming trace data to a peripheral device location.

ATB input32-bits8-bits2 x 8 bit32-bits, 128 bits
Parallel Trace Port

2, 4, 8, 16, or 32 data pins

1 clock pin

1 control pin


1, 2, or 4 data pins

1 clock pin

No. Data is output over AXI at the same width as ATB input.
Serial Wire OutputNoManchester or NRZ encodedManchester or NRZ encodedNo
Data StorageNoneNoneNoneNone
Memory Footprint4KB4KB4KB4KB
Designer IDARM (0x43B)ARM (0x43B)ARM (0x43B)ARM (0x43B)
Part number0x9410x9140x9230x961
Device ID0x0000xEA00xCA0 or 0xCA1Configurable
Dev Type0x110x110x110x21
Lock Access RegisterBypassableBypassableNoBypassable
Claim Tags4-bits4-bits4-bits4-bits
Topology detectionYesYesYesYes
Integration registersYesYesNoYes

[a] The ETR is a configuration option of the Trace Memory Controller (TMC).

Copyright © 2004, 2007, 2010 ARM Limited. All rights reserved.ARM DGI 0012D