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Table 3.7 and Table 3.8 shows the sink component features.
Table 3.7. Sink component features, part 1
| Component name | ETB11 | TPIU | CS ETB | ETB[a] |
|---|---|---|---|---|
| CoreSight compliant | No | Yes | Yes | Yes |
| Description | Onchip trace capture device for capture of non-CoreSight legacy ETMs. | Parallel trace port for interfacing on-chip trace to off-chip capture devices. | Provides on-chip storage of trace data | Provides on-chip storage of trace data in a local SRAM. |
| Features | - | Includes pattern generation for thorough analysis of pin timing. | - | Includes programmable mode to use the SRAM as a FIFO when taking data over the Debug APB interface. |
| ATB input | Non-applicable | 32 bit | 32 bit | 32-bits to 128-bits |
| Parallel Trace Port | No | 1-32 data pins 1 clock pin 1 optional control pin | No | No |
| Serial Wire Output | No | No | No | No |
| Data Storage | 1KB to 1MB | None | 1 KB to 1 MB | 1KB to 4GB |
| Formatter | Non-applicable | Yes | Yes | Yes |
| Memory Footprint | 4KB + Memory size | 4KB | 4KB | 4KB |
| Designer ID | Non-applicable | ARM (0x43B) | ARM (0x43B) | ARM (0x43B) |
| Part number | Non-applicable | 0x912 | 0x907 | 0x961 |
| Device ID | Non-applicable | 0x0A0 | 0x000 | Configurable |
| Dev Type | Non-applicable | 0x11 | 0x21 | 0x21 |
| Lock Access Register | No | Bypassable | Bypassable | Bypassable |
| Claim Tags | None | 4 bits | 4 bits | 4-bits |
| Topology detection | No | Yes | Yes | Yes |
| Integration registers | No | Yes | Yes | Yes |
[a] The ETB is a configuration option of the Trace Memory Controller (TMC). | ||||
Table 3.8. Sink component features, part 2
| Component name | TPIU-Lite | SWO | CM3 TPIU | Embedded Trace Router (ETR)[a] |
|---|---|---|---|---|
| CoreSight compliant | Yes | Yes | Yes | Yes |
| Description | Low gate count parallel trace interface between on-chip trace and off-chip capture devices. | Serial Wire output for Instrumentation Trace Macrocell trace to off-chip capture devices. | Cortex-M3 specific, parallel and serial trace interface to off-chip trace capture devices. | Provides on-chip storage of trace data in the system through an AXI interface. |
| Features | - | - | Includes trace funnel | Contains the following modes of using the system memory:
|
| ATB input | 32-bits | 8-bits | 2 x 8 bit | 32-bits, 128 bits |
| Parallel Trace Port | 2, 4, 8, 16, or 32 data pins 1 clock pin 1 control pin | No | 1, 2, or 4 data pins 1 clock pin | No. Data is output over AXI at the same width as ATB input. |
| Serial Wire Output | No | Manchester or NRZ encoded | Manchester or NRZ encoded | No |
| Data Storage | None | None | None | None |
| Formatter | No | No | Yes | Yes |
| Memory Footprint | 4KB | 4KB | 4KB | 4KB |
| Designer ID | ARM (0x43B) | ARM (0x43B) | ARM (0x43B) | ARM (0x43B) |
| Part number | 0x941 | 0x914 | 0x923 | 0x961 |
| Device ID | 0x000 | 0xEA0 | 0xCA0 or 0xCA1 | Configurable |
| Dev Type | 0x11 | 0x11 | 0x11 | 0x21 |
| Lock Access Register | Bypassable | Bypassable | No | Bypassable |
| Claim Tags | 4-bits | 4-bits | 4-bits | 4-bits |
| Topology detection | Yes | Yes | Yes | Yes |
| Integration registers | Yes | Yes | No | Yes |
[a] The ETR is a configuration option of the Trace Memory Controller (TMC). | ||||
| Copyright © 2004, 2007, 2010 ARM Limited. All rights reserved. | ARM DGI 0012D |
| Non-Confidential | ID062610 |
| PDF version | |
| Home > Features of CoreSight Technology and ETM Architectures > CoreSight component data > Sink features |