CoreSight™ Technology System Design Guide

Table of Contents

About this guide
Product revision status
Intended audience
Using this guide
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About CoreSight systems
1.2. CoreSight features
1.2.1. Debug access
1.2.2. Cross Triggering
1.2.3. Trace
2. CoreSight Components and Systems
2.1. About CoreSight systems and components
2.2. CoreSight components
2.2.1. Buses
2.2.2. Control and access components
2.2.3. Trace sources
2.2.4. Trace links
2.2.5. Trace sinks
2.2.6. External debug hardware and software
2.3. CoreSight system examples
2.3.1. Single core debug
2.3.2. Single source trace
2.3.3. Multi source trace in an single CPU system
2.3.4. Multi source trace in a multi-core system
2.4. Illegal structures
2.4.1. Stacked DAPs
2.4.2. Duplicated IDs
2.4.3. Feedback of source ID and data duplication
3. Features of CoreSight Technology and ETM Architectures
3.1. About CoreSight Technology and ETM architectures features
3.2. CoreSight component data
3.2.1. DAP features
3.2.2. Source features
3.2.3. Link features
3.2.4. Sink features
3.2.5. Debug features
3.3. Architectural features of ARM trace sources
4. Debug Access
4.1. About debug access
4.2. Access to the system
4.2.1. JTAG direct to core access
4.2.2. DAP access
4.3. Access to debug components
4.3.1. Debug memory overview
4.3.2. System interface
4.3.3. Debug memory decoding and the ROM table
4.3.4. Example memory system
4.3.5. Example memory map
4.4. Mixed legacy and DAP debug
4.4.1. Mixing JTAG devices with JTAG-DP
4.4.2. Mixing JTAG devices with SWJ-DP
4.5. Debug activity across the chip
4.5.1. Direct links
4.5.2. Linking with an ECT
4.6. Typical trigger signals
4.6.1. CPU connections
4.6.2. ETM connections
4.6.3. Other trace source connections
4.6.4. TPIU and ETB connections
5. Trace Capture
5.1. About trace capture
5.1.1. Operation of a TCD
5.2. Designing your trace system
5.2.1. Differences between on-chip and off-chip storage
5.2.2. Calculating the number of trace port pins
5.2.3. Calculating the size of on-chip RAM required
5.2.4. ATB bandwidth
5.2.5. Using additional buffers in trace systems
5.3. Using your system
5.3.1. Synchronization frequency
5.3.2. Using the ETB for profiling
5.3.3. Arbitration
6. Implementation
6.1. About implementation
6.2. Power control
6.2.1. Multiple power domains
6.2.2. Intelligent Energy Management (IEM)
6.3. Power domains and system design
6.4. Power control enabled components
6.4.1. Debug Access Port (DAP)
6.4.2. Power for Trace Sources, ETM11CS, ETM9CS, and HTM
6.5. Debug and system power up
6.6. Clock domains
6.6.1. CoreSight system clock design
6.6.2. Clocking in an power control enabled system
6.6.3. CoreSight clocks and their inter-relationships
6.7. Resets
6.7.1. Connection of CSDK resets
6.7.2. Example CoreSight configurations
6.8. Tools controlled debug reset
6.9. Interface timing
6.9.1. Recommended ATB master interface timing parameters
6.9.2. Recommended ATB slave interface timing parameters
6.10. Timing, synthesis, and placement
6.10.1. DAP placement
6.10.2. ATB 1:1 bridge synthesis
6.10.3. TPIU TRACECLK generation
A. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. DAP connections inside a SoC
1.2. Cross triggering
1.3. Example system with trace components
2.1. CoreSight system components
2.2. Structure of the CoreSight DAP component
2.3. HTM connected to a multi-layer AHB system
2.4. TPIU block diagram
2.5. ETB block diagram
2.6. Single CPU trace and Debug APB debug access
2.7. Single source trace with the TPIU formatting bypass
2.8. Full CoreSight trace with single core
2.9. Full system trace with ARM core and CoreSight compliant DSP
2.10. Unsupported DAP connection
2.11. Unsupported replicator and funnel connection
2.12. Unsupported feedback loop
4.1. JTAG connection
4.2. Example memory system for access to debug components
4.3. Example memory map for access to debug components
4.4. JTAG core connected in parallel with DAP
4.5. An example JTAG connection
4.6. Processor interaction
4.7. Signals of interest
5.1. Example system with ETB and TPIU
5.2. Use of the trigger to set a trace window
5.3. Effect of FIFO size on required trace bandwidth
5.4. System with two ETBs
5.5. Using additional buffers for trace system
5.6. Effect of frequency compared with infrequent synchronization points
6.1. CoreSight system with no separate debug domains
6.2. CoreSight system with a separate debug power domain
6.3. ETM power and voltage domains
6.4. Unified power and voltage domains for ETM
6.5. HTM power and voltage domains
6.6. Unified power and voltage domains for HTM
6.7. Power-up request and acknowledgement timing
6.8. Clock domain interactions
6.9. Synchronous example clock configuration
6.10. Asynchronous example clock configuration
6.11. Reset handshaking mechanism
6.12. ATB master interface timing
6.13. ATB slave interface timing
6.14. Balancing TRACECLK
6.15. Timing balance

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision Non-Confidential29 September 2004First release
Revision Non-Confidential20 July 2007Updated for r1p0
Revision Non-Confidential29 April 2010Updated for STM and TMC
Revision Non-Confidential25 June 2010Update on Clock domain interactions
Copyright © 2004, 2007, 2010 ARM Limited. All rights reserved.ARM DGI 0012D