2.2.5. Transaction latency regulation

The feedback control regulator achieves transaction latency regulation by modifying the AxQOS value of each transaction request. This overrides any AxQOS value that the NIC-400 base product might have specified. If the interconnect and the addressed slave treat this as a priority value, then it has the required regulatory effect. For example, if a transaction is given an AxQOS value that gives it a higher priority, then this tends to reduce the transaction latency of that transaction. In this way, a feedback loop is set up so that when the actual latency is higher than the target transaction latency, the AxQOS value is proportionately raised, and the larger the transaction latency discrepancy, the higher the priority.


AxQOS is either ARQOS or AWQOS.

Transaction latency regulation is useful for masters that have performance that is directly dependent on transaction latency. For example, a processor might be stalled while it waits for data after a cache miss.

You program the target transaction latency separately for writes and reads. You enable transaction latency regulation by setting the appropriate control bits in the QoS control register. See QoS Control Register.

When you enable transaction latency regulation for reads or writes, the base product AxQoS values are not used.

You set the range of AxQOS values used for transaction latency regulation by programming the minimum and maximum values for writes and reads.

You program a scaling factor to give control over how quickly the AxQOS values change. The smaller the scaling factor, the more slowly the AxQOS values change in response to changes in transaction latency. The scaling factor is specified in powers of two. See Feedback Controlled Scale Register.

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