3.2. Register summary

Table 3.1 shows the registers in offset order from the base memory address.

Table 3.1. Register summary

Offset

Name

Type

Reset

Width

Description

0x000-0x0FF----Reserved
0x100read_qosRW04CoreLink NIC-400 Network Interconnect read_qos register. See the ARM® CoreLink™ NIC-400 Network Interconnect Technical Reference Manual for information about this register.
0x104write_qosRW04CoreLink NIC-400 Network Interconnect write_qos register. See the ARM® CoreLink™ NIC-400 Network Interconnect Technical Reference Manual for information about this register.
0x108fn_modRW02CoreLink NIC-400 Network Interconnect fn_mod register. See the ARM® CoreLink™ NIC-400 Network Interconnect Technical Reference Manual for information about this register.
0x10Cqos_cntlRW02,8QoS Control Register.
0x110max_otRW06, 8, 6, 8Maximum Number of Outstanding Transactions Register.
0x114max_comb_otRW07, 8Maximum Combined Outstanding Transactions Register.
0x118aw_pRW08AW Channel Peak Rate Register.
0x11Caw_bRW016AW Channel Burstiness Allowance Register.
0x120aw_rRW012AW Channel Average Rate Register.
0x124ar_pRW08AR Channel Peak Rate Register.
0x128ar_bRW016AR Channel Burstiness Allowance Register.
0x12Car_rRW012AR Channel Average Rate Register.
0x130

target_fc

RW012, 12Feedback Controlled Target Register.
0x134ki_fcRW03, 3Feedback Controlled Scale Register.
0x138qos_rangeRW04, 4, 4, 4QoS Range Register.
0x13C-0xFFF----Reserved.

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