3.3.8. AR Channel Burstiness Allowance Register

The ar_b Register characteristics are:


This register enables you to program a burstiness allowance, in number of transfers. See Transaction rate regulation for more information.

Usage constraints

There are no usage constraints.


Only available when you select transaction rate regulation in AMBA Designer.


Figure 3.8 shows the bit assignments.

Figure 3.8. ar_b Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 3.9 shows the bit assignments.

Table 3.9. ar_b Register bit assignments

[31:16]-Reserved. Do not modify. Read as zero.
[15:0]ar_bAR channel burstiness.

Copyright © 2012, 2013 ARM. All rights reserved.ARM DSU 0026C