3.3.1. QoS Control Register

The qos_cntl Register characteristics are:

Purpose

This register contains the enable bits for all the regulators. By default, all of the bits are set to 0, and no regulation is enabled.

Usage constraints

Regulation only takes place when both the enable bit is set, and its corresponding regulation value is non-zero. This enables you to perform an integration test without activating the regulation.

The QoS regulators are reset whenever they are re-enabled. The transaction and address latency regulator enables en_ar_fc and en_aw_fc can be used to provide a soft reset of these regulators. If the values in the qos_range register are changed to make the range narrower than either the previous upper or lower bounds then you must reset the regulator through a soft reset by disabling and re-enabling it. If the values in the qos_range register are changed to make the range wider than either the previous upper or lower bounds then the regulator does not require a soft reset.

Configurations

Available in all QoS-400 configurations.

Attributes

Figure 3.1 shows the bit assignments.

Figure 3.1. qos_cntl Register bit assignments

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Table 3.2 shows the bit assignments.

Table 3.2. qos_cntl Register bit assignments

BitsNameFunction
[31:21]-Reserved. Do not modify. Read as zero.
[20]mode_ar_fc

Select feedback control regulation for AR of either transaction or address latency as follows:

0b0

Transaction latency.

0b1

Address latency.

[19:17]-Reserved. Do not modify. Read as zero.
[16]mode_aw_fc

Select feedback control regulation for AW of either transaction or address latency as follows:

0b0

Transaction latency.

0b1

Address latency.

[15:8]-Reserved. Do not modify. Read as zero.
[7]en_awar_ot[a]Enable combined regulation of outstanding transactions.
[6]en_ar_ot[a]Enable regulation of outstanding read transactions.
[5]en_aw_ot[a]Enable regulation of outstanding write transactions.
[4]en_ar_fc[b]Enable regulation of AR transaction or address latency using feedback control, depending on the value to which you set mode_ar_fc.
[3]en_aw_fc[b]Enable regulation of AW transaction or address latency using feedback control, depending on the value to which you set mode_aw_fc.
[2]en_awar_rate[c]Enable combined AW and AR rate regulation.
[1]en_ar_rate[c]Enable AR rate regulation.
[0]en_aw_rate[c]Enable AW rate regulation.

[a] If you include outstanding transaction regulation, you can configure en_awar_ot, en_ar_ot, and en_aw_ot. Otherwise, bits [7:5] are reserved, read as zero, and you cannot modify them.

[b] If you include transaction or address latency regulation, you can configure en_ar_fc and en_aw_fc. Otherwise, bits [4:3] are reserved, read as zero, and you cannot modify them.

[c] If you include transaction rate regulation, you can configure en_awar_rate, en_ar_rate, and en_aw_rate. Otherwise, bits [2:0] are reserved, read as zero, and you cannot modify them.


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