2.2.3. Transaction rate regulation

A variant of the standard internet Traffic SPECification (TSPEC) specifies transaction rate regulation using the following parameters:

p

Peak rate.

b

Burstiness allowance.

r

Average rate.

You can independently program and enable the regulation of the read and write address channels with their own control bits. Alternatively, you can select combined regulation of the read and write address channels using another control bit. See Chapter 3 Programmers Model.

The request arrival curve, that graph (A) TSPEC traffic upper bound shows, in Figure 2.3 represents the characteristics imposed on the request flow, or flows.

Figure 2.3. TSPEC traffic specification

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The TSPEC parameters define an upper bound that applies over any time window.

(B) Traffic bounded by TSPEC in Figure 2.3 illustrates this, with the accumulated data curve bounded by the TSPEC curve from any point in the data sequence. You program the TSPEC parameter values for AW and AR request rates in separate sets of registers. See Chapter 3 Programmers Model.

The regulators are disabled after reset.

If you program the regulators while they are enabled, the new values take effect immediately. Alternatively, you can disable the regulators, update the values, and then re-enable the regulators.

Binary fractions in transfers per cycle provide the values for peak and average rates.

So, for example, a value of 0x800, that is, 0.5 in decimal, sets a rate of one transfer every two cycles.

A value of 0x100, that is, 0.0625 in decimal, sets a rate of one transfer every 16 cycles.

A value of 0x000 sets a rate of one transfer per cycle, that is, no regulation. If you set either the burstiness to 0, or the average rate to 0, this disables the regulation of burstiness and average rate, (b,r).

In the same way, if you set the peak rate to 0, this disables the peak rate regulation. You can set:

Example 2.3. How to program the TSPEC regulator registers

This example describes a case where you set the following requirements:

  • Transaction rate to use 4% of the available bandwidth.

  • Each transaction to be a 16-beat burst.

  • Peak rate, p.

  • Burstiness allowance, b.

  • Average rate registers, r.

It must be noted that the burstline allowance is not related to the AXI burst length. It is a measure of traffic burstiness, in this case the burstiness of transfers on the AW or AR channels.

Transactions are regulated on AW and AR transfers, so you can use the burst length to calculate the AR or AW transfer rate from the required bandwidth as follows:

  • The required data bandwidth is 4% that is equal to four data transfers in every 100 cycles.

  • One transaction has 16 beats of data, so requires one transaction every 16/4 * 100 cycles. This gives one transaction every 400 cycles.

One transfer every 400 clock cycles is equivalent to 0.0025 transfers per cycle. You must convert this into a 12 bit binary fraction to give the value to program the average rate register with:

0b000000001010

This value is an approximation limited in accuracy by the number of bits available in the average rate register.

This value is an approximation limited in accuracy by the number of bits available in the average rate register. See AW Channel Average Rate Register and AR Channel Average Rate Register. In this example, the nearest approximation gives a rate of 1 transaction every 409.6 clock cycles or 16/409.6*100 = 3.9% of available bandwidth. If you do not set all three TSPEC values, you can set either the peak rate only, or the burstiness and average rate, without the peak rate.

The peak rate register, p is only 8 bits, not 12 bits as in the average rate register, r, so the previously calculated value does not fit. See AW Channel Average Rate Register and AR Channel Average Rate Register. Therefore, you can achieve hard regulation at one transaction in 409 clock cycles by setting the following:

The burstiness allowance, combined with the peak rate and average rate, enables variance in the issuing rate from that master during different system loadings. For example, set the values as follows:

This permits a maximum issuing rate of one request every 256 clock cycles until the burstiness allowance, b, has been used up, and then, a maximum issuing rate, r, of one request every 409.6 clock cycles.

The regulator keeps track of the burstiness allowance to control whether the issuing rate is limited to the peak rate, p, or to the average rate, r. The burstiness allowance is initialized from the burstiness allowance register, b. When regulation is enabled it is decremented on every transfer and incremented at the average rate. While the allowance is non-zero the peak rate is allowed. In this example, the burstiness allowance starts at 5, so, at the peak issuing rate, the allowance reaches 0 after:

b * (p/(p-r)) = 5 * (O.0039/(0.0039 - 0.00244) = 13 transfers

When the allowance has reached zero the issuing rate is limited to the average rate. If the issuing rate from the master drops below the average rate, then the burstiness allowance increases until it reaches the programmed burstiness allowance, b.


Note

To calculate the 12-bit binary from the decimal fraction use the following equation:

<12-bit binary fraction> = 12^12 * <decimal fraction> = 4096 * <decimal fraction>

For example, converting the decimal fraction 0.0025, would give 4096 * 0.0025 or 10.24. Rounding this to the nearest whole number gives 10 or 0b0000 0000 1010 as a 12-bit binary number.

Combined AW and AR transaction rate regulation

You can regulate the combined transaction rate from the AW and AR channels. When you select this mode, QoS ignores the individual channel rates. QoS takes the TSPEC parameter values for the AW and AR channels from the values programmed in the AW registers. See Chapter 3 Programmers Model.

Because two channels support twice the rate of a single channel, QoS scales the TSPEC parameters, for combined regulation, by a factor of two. For example, to specify a combined average rate of one transfer every eight cycles, set the value to 0x100. This is equal to two transfers every 16 cycles. That is, the rate you program is half the required combined rate.

When the combined AW and AR channel traffic is so close to the TSPEC boundary that only one transfer is permitted, but both channels are requesting, then the regulator admits the AW channel and AR channel alternately.

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