2.2.6. Address request latency regulation

The feedback control regulator achieves address request latency regulation by modifying the axqos value of each transaction request. This overrides any axqos value that the base product has specified. If the interconnect and the addressed slave treat this as a priority value, then it has the required regulatory effect. For example, if a transaction is given an axqos value that gives it a higher priority, then this reduces the latency between address requests. In this way, a feedback loop is set up so that when the actual latency is higher than the target latency, the axqos value is proportionately raised, and the larger the latency discrepancy, the higher the priority.


  • The regulator measures the time between address requests.

  • axqos is either arqos or awqos.

Address request period regulation is useful for masters that have minimum bandwidth requirements, for example, a GPU.

You program the target period separately for writes and reads. You enable address request period regulation by setting the appropriate control bits in the QoS control register. See QoS Control Register.

When you enable address request period regulation for reads or writes, the base product axqos values are not used. When you disable address request period regulation, the base product axqos values are passed through unmodified.

You set the range of axqos values used for address request period regulation by programming the minimum and maximum values for writes and reads.

You program a scaling factor to give control over how quickly the axqos values change. The smaller the scaling factor, the more slowly the axqos values change in response to changes in latency. The scaling factor is specified in powers of two. See Feedback Controlled Scale Register.

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