2.1.3. Low-power interface

This section describes:

Hierarchical clock gating interfaces

When the TLX bridge is configured to support hierarchical clock gating there is a Low-power Interface (LPI) to enable clock gating of the master interface clock domain. See the ARM® AMBA® AXI™ and ACE Protocol Specification for more information on the LPI.

When the LPI indicates that the low-power state has been entered then the clock for the master interface domain can be clock gated.

When the TLX bridge is configured to support hierarchical clock gating, there is a cactive signal output from the slave clock domain to assist in clock gating of the slave interface domain. It is driven HIGH when the TLX requires the clock, and must be incorporated in the slave interface clock domain clock controller.

Power domain crossing interfaces

When a bridge is configured to support Power Domain Crossing (PDC), hierarchical clock gating support is also included.

An additional PDC LPI is output from the slave domain to support the power gating sequence. When the PDC LPI is changing mode of operation, the slave domain clock must be operational. The bridge slave domain asserts an additional LPI cactive signal, to indicate that a clock is required and must not be turned off.

If the PDC LPI indicates that the low-power state has been entered, either power domain can be power gated.

Note

If the master domain is powered down, any transactions issued to the slave domain are stalled at the interface.

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