2.1.5. Signal descriptions

The interface signals are listed in Table 2.1. For additional information on these signals see the ARM® AMBA® 4 AXI4-Stream Protocol Specification.

Table 2.1 uses the following parameters to define the signal widths:

Where:

n

Data bus width in bits.

m

Flow control bus width in bits. For a forward Physical Layer (PL):

For an AHB TLX-400 bridge:

The flow control bus width = 1.

For an AXI TLX-400 bridge:

The flow control bus width = 2.

For an AXI TLX-400 bridge with QVN AMBA quality of service using virtual networks:

The flow control bus width = 2 * number of virtual networks.

Table 2.1. Forward PL interface signal descriptions

Signal NameDescription
pl_fwd_x_tlxclkThis is the clock source and the global clock signal. All signals are sampled on the rising edge of pl_fwd_x_tlxclk.
pl_fwd_x_tresetnThis is the reset source and the global reset signal. pl_fwd_x_tresetn is active-LOW.
tvalid_pl_fwd_x_s_streamIndicates a valid data transfer is being presented to the forward PL.
tdata_pl_fwd_x_s_stream[(n-1):0] This is the data payload input.
tready_pl_fwd_x_s_streamIndicates that the slave can accept a transfer in the current cycle.
tvalid_pl_fwd_x_m_streamIndicates that the forward physical layer is presenting a valid data transfer to the forward Data Link Layer (DLL).
tdata_pl_fwd_x_m_stream[(n-1)]:0]This is the data payload output.
tready_pl_fwd_x_m_streamIndicates that the forward data link layer can accept a transfer in the current cycle.
tvalid_pl_fwd_x_s_flowIndicates a valid flow control transfer is being presented to the forward PL.
tdata_pl_fwd_x_s_flow[(m-1):0]This is the flow control payload input.
tready_pl_fwd_x_s_flowIndicates that the slave can accept a transfer in the current cycle.
tvalid_pl_fwd_x_m_flowIndicates that the forward physical layer is presenting a valid flow control transfer to the forward DLL.
tdata_pl_fwd_x_m_flow[(m-1):0]This is the flow control payload output.
tready_pl_fwd_x_m_flowIndicates that the forward data link layer can accept a transfer in the current cycle.

Table 2.2 uses the following parameters to define the signal widths:

Where:

n

Data bus width in bits.

m

Flow control bus width in bits. For a reverse physical layer:

For an AHB TLX-400 bridge:

The flow control bus width = 2.

For an AXI TLX-400 bridge:

The flow control bus width = 3.

For an AXI TLX-400 bridge with QVN AMBA quality of service using virtual networks:

The flow control bus width = 3 * number of virtual networks.

Table 2.2. Reverse PL interface signal descriptions

Signal NameDescription
pl_rev_x_tlxclkThis is the clock source and the global clock signal. All signals are sampled on the rising edge of pl_rev_x_tlxclk.
pl_rev_x_tresetnThis is the reset source and the global reset signal. pl_rev_x_tresetn is active-LOW.
tvalid_pl_rev_x_s_streamIndicates a valid data transfer is being presented to the reverse PL.
tdata_pl_rev_x_s_stream[(n-1):0] This is the data payload input.
tready_pl_rev_x_s_streamIndicates that the slave can accept a transfer in the current cycle.
tvalid_pl_rev_x_m_streamIndicates that the reverse physical layer is presenting a valid data transfer to the reverse DLL.
tdata_pl_rev_x_s_flow[(m-1):0]This is the data payload output.
tready_pl_rev_x_m_streamIndicates that the reverse data link layer can accept a transfer in the current cycle.
tvalid_pl_rev_x_s_flowIndicates a valid flow control transfer is being presented to the reverse PL.
tdata_pl_rev_x_s_flow[(m-1):0]This is the flow control payload input.
tready_pl_rev_x_s_flowIndicates that the slave can accept a transfer in the current cycle.
tvalid_pl_rev_x_m_flowIndicates that the reverse physical layer is presenting a valid flow control transfer to the reverse DLL.
tdata_pl_rev_x_m_flow[(m-1):0]This is the flow control payload output.
tready_pl_rev_x_m_flowIndicates that the reverse data link layer can accept a transfer in the current cycle.

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