| Copyright © 2004, 2005 ARM Limited. All rights reserved. | ARM DTO 0008B |
| Non-Confidential | |
 PDF version | |
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Table 1.1 lists the AXI master interface attributes.
Table 1.1. AXI master interface attributes
Attribute | Description | Value |
|---|---|---|
Combined issuing capability | The maximum number of active transactions that a master can generate | 1 |
Write ID capability | The maximum number of different AWID values that a master can generate for all active write transactions at any one time | 1 |
Write ID width | The number of bits in the AWID, WID, and BID buses | 0 |
Read ID capability | The maximum number of different ARID values that a master can generate for all active read transactions at any one time | 1 |
Read ID width | The number of bits in the ARID and RID buses | 0 |
| Copyright © 2004, 2005 ARM Limited. All rights reserved. | ARM DTO 0008B |
| Non-Confidential | |
| PDF version | |
| Home > PrimeCell® Infrastructure AMBA™ 2 AHB™ to AMBA 3 AXI™ Bridges (BP136) > About the AHB to AXI bridges > AXI master interface attributes |