3. Functional description

Figure 2 shows a block diagram of the major internal component blocks.

Figure 2. AXI downwards-synchronizing bridge components

The major internal component blocks are:

SyncDnAxiHshk

This is an AXI downwards-synchronizing handshake block. The inputs and outputs are not registered. The block synchronizes the valid and ready signal handshakes in a system where the transfer source component is clocked at a higher frequency than the transfer destination component. The clock domains must be synchronously related so that the clock select occurs over the coincidental rising edges.

The SyncDnAxiHshk block is used for the AXI channels shown in Figure 2.

SyncUpAxiChan

This is an AXI upwards-synchronizing channel block. The inputs and outputs are not registered. The block synchronizes the valid and ready signal handshakes in a system where the transfer source component is clocked at a lower frequency than the transfer destination component. A zero latency buffer is used to synchronize the write response and read channels. The clock domains must be synchronously related so that the clock select occurs over the coincidental rising edges.

The SyncUpAxiHshk block is used for the AXI channels shown in Figure 2.

SyncLwPwrIf

The AXI low-power signaling mechanism provides a coherent control method for a system-level power-down mode.

For systems that require multiple related clock domains, a low-power mode-aware component can sit in a different clock domain to that of the system low-power controller. The synchronizing low-power interface, SyncDnLwPwrIf, ensures that transfers across these boundaries can complete. The interface retimes the CSYSREQ, CSYSACK, and CACTIVE signals between the clock domains. All low-power channel signals are retimed to supply a definite timing point for implementation, and to ensure satisfactory synchronization in both domains.

See the AMBA AXI Protocol Specification for more information.

Copyright © 2004 ARM Limited. All rights reserved.ARM DTO 0011A
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