3.2. Interface attributes
The master and slave interface attributes for the AXI register
slice are described in:
Table 2. Master interface attributes
| Attribute | Description | Value |
|---|
| Write ID capability | The maximum number of different AWID values that a master can generate
for all active write transactions at any one time | Master-dependent |
| Write ID width | The number of bits in the AWID and WID buses. | Master-dependent |
| Write issuing capability | The maximum number of active write transactions
that a master can generate. | Master-dependent |
| Read ID capability | The maximum number of different ARID values that a master can generate
for all active read transactions at any one time. | Master-dependent |
| Read ID width | The number of bits in the ARID bus. | Master-dependent |
| Read issuing capability | The maximum number of active read transactions
that a master can generate. | Master-dependent |
Table 3. Slave interface attributes
| Attribute | Description | Value |
|---|
| Write acceptance capability | The maximum number of active write transactions
that a slave can accept. | Slave-dependent |
| Read acceptance capability | The maximum number of active read transactions
that a slave can accept. | Slave-dependent |
| Write interleave depth | The number of active write transactions for
which the slave can receive data. This is counted from the earliest
transaction. | Slave-dependent |
| Read data reorder depth | The number of active read transactions for
which a slave may transmit data. This is counted from the earliest
transaction. | Slave-dependent |
Note
Master-dependent and slave-dependent used in the Value column
of Table 2 and Table 3 mean that the
register slice adopts the attribute value of the master or slave that
the relevant interface is connected to.
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