5.4. Non-standard signals

Table 5 lists signals that are present on the register slice but are not described in the AXI specification.

Table 5. Non-standard signals (continued)

NameType

Source/

destination

Description
SCANENABLEInputScan logicScan mode enable
SCANINACLKInputScan logicScan chain input
SCANOUTACLKOutputScan logicScan chain output
AWUSERSInputAXI masterAdditional sideband signals for the write address channel
WUSERSInputAXI masterAdditional sideband signals for the write data channel
BUSERSOutputAXI masterAdditional sideband signals for the write response channel
ARUSERSInputAXI masterAdditional sideband signals for the read address channel
RUSERSOutputAXI masterAdditional sideband signals for the read data channel
AWUSERMOutputAXI slaveAdditional sideband signals for the write address channel
WUSERMOutputAXI slaveAdditional sideband signals for the write data channel
BUSERMInputAXI slaveAdditional sideband signals for the write response channel
ARUSERMOutputAXI slaveAdditional sideband signals for the read address channel
RUSERMInputAXI slaveAdditional sideband signals for the read data channel
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