2. About the AXI asynchronous bridge

The AXI asynchronous bridge, AsyncAxi, enables two AXI clock domains to communicate. Figure 1 shows AsyncAxi with data being transferred between two AXI clock domains.

Figure 1. Asynchronous bridge block diagram

The bridge provides buffered synchronization of the AXI channels:

AW

Write address channel.

W

Write data channel.

B

Write response channel.

AR

Read address channel.

R

Read data channel.

The HDL code is supplied as Verilog.

The major features of the bridge are:

The PrimeCell Infrastructure AMBA 3 AXI Asynchronous Bridge (BP132) Design Manual provides more information about these features.

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