5.2.7. Thumb instruction set overview

The functionality of the Thumb instruction set, with one exception, is a subset of the functionality of the ARM instruction set. The instruction set is optimized for production by a C compiler.

All Thumb instructions are 16 bits long and are stored halfword aligned in memory. Because instructions are stored halfword-aligned, the bottom bit of the address of an instruction is always set to zero in Thumb state. This bit is ignored by all Thumb instructions that have an address operand except for the Branch Exchange (BX) instruction.

All Thumb data processing instructions:

In general, the Thumb instruction set differs from the ARM instruction set in the following ways. Refer to the ARM Architectural Reference Manual for detailed information on the syntax of the Thumb instruction set, and how Thumb instructions differ from their ARM counterparts:

Branch instructions

These instructions are used to branch backwards to form loops, to branch forward in conditional structures, to branch to subroutines, and to change the processor from Thumb state to ARM state. Program-relative branches, particularly conditional branches, are more limited in range than in ARM code, and branches to subroutines can only be unconditional.

Data processing instructions

These operate on the general purpose registers. The result of the operation is put in one of the operand registers, not in a third register. There are fewer data processing operations available than in ARM state. They have limited access to registers r8 to r15.

The ALU status flags in the CPSR are always set by these instructions except when MOV or ADD instructions access registers r8 to r15. Thumb data processing instructions that access registers r8 to r15 cannot set the flags.

Status register access instructions

There are no Thumb instructions to access the CPSR or SPSR.

Single register load and store instructions

These instructions load or store the value of a single low register from or to memory. In Thumb state they cannot access registers r8 to r15.

Multiple register load and store instructions

These instructions load from memory or store to memory any subset of the registers in the range r0 to r7.

In addition, the PUSH and POP instructions implement a full descending stack using the stack pointer (r13) as the base. PUSH can stack the link register and POP can load the program counter.

Semaphore instructions

There are no Thumb semaphore instructions.

Coprocessor instructions

There are no Thumb coprocessor instructions.

Thumb instruction capabilities

The following general points apply to Thumb instructions:

Conditional execution

The conditional branch instruction is the only Thumb instruction that can be executed conditionally on the value of the ALU status flags in the CPSR. All data processing instructions set these flags, except when one or more high registers are specified as operands to the MOV or ADD instructions. In these cases the flags cannot be set.

You cannot have any data processing instructions between an instruction that sets a condition and a conditional branch that depends on it. You must use conditional branches over any instructions that you wish to be conditional.

Register access

In Thumb state, most instructions can access only r0-r7. These are referred to as the low registers.

Registers r8 to r15 are limited access registers. In Thumb state these are referred to as high registers. They can be used, for example, as fast temporary storage.

Refer to the ARM Architectural Reference Manual for a complete list of the Thumb data processing instructions that can access the high registers.

Access to the barrel shifter

In Thumb state you can use the barrel shifter only in a separate operation, using an LSL, LSR, ASR, or ROR instruction.

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