9.11.2. The return address

If an exception occurs in ARM state, the value stored in lr_mode is (pc – 4) as described in The return address and return instruction. However, if the exception occurs in Thumb state, the processor automatically stores a different value for each of the exception types. This adjustment is required because Thumb instructions take up only a halfword, rather than the full word that ARM instructions occupy.

If this correction were not made by the processor, the handler would have to determine the original state of the processor, and use a different instruction to return to Thumb code rather than ARM code. By making this adjustment, however, the processor allows the handler to have a single return instruction that will return correctly, regardless of the processor state (ARM or Thumb) at the time the exception occurred.

The following sections give a summary of the values to which the processor sets lr_mode if an exception occurs when the processor is in Thumb state.

SWI and Undefined instruction handlers

The handler's return instruction (MOVS pc,lr) changes the program counter to the address of the next instruction to execute. This is at (pc – 2), so the value stored by the processor in lr_mode is (pc – 2).

FIQ and IRQ handlers

The handler's return instruction (SUBS pc,lr,#4) changes the program counter to the address of the next instruction to execute. Because the program counter is updated before the exception is taken, the next instruction is at (pc – 4). The value stored by the processor in lr_mode is therefore pc.

Prefetch abort handlers

The handler's return instruction (SUBS pc,lr,#4) changes the program counter to the address of the aborted instruction. Because the program counter is not updated before the exception is taken, the aborted instruction is at (pc – 4). The value stored by the processor in lr_mode is therefore pc.

Data abort handlers

The handler's return instruction (SUBS pc,lr,#8) changes the program counter to the address of the aborted instruction. Because the program counter is updated before the exception is taken, the aborted instruction is at (pc – 6). The value stored by the processor in lr_mode is therefore (pc + 2).

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