9.11.3. Determining the processor state

An exception handler may need to determine whether the processor was in ARM or Thumb state when the exception occurred. SWI handlers, especially, may need to read the processor state. This is done by examining the SPSR T bit. This bit is set for Thumb state and clear for ARM state.

Both ARM and Thumb instruction sets have the SWI instruction. We have already examined how to handle SWIs called from ARM state (in SWI handlers). Here we address the handling of SWIs that are called from Thumb state. When doing so there are three considerations to bear in mind:

Figure 9.5. Thumb SWI instruction

Thumb SWI instruction

Example 9.18 shows ARM code that handles a SWI from both sources. Note the following points:

Example 9.18. 

T_bit		EQU	0x20							; Thumb bit of CPSR/SPSR, that is, bit 5.
		STMFD		sp!, {r0-r3,lr}						; Store the registers.
		MRS 		r0, spsr 						; Move SPSR into general purpose 
										; register.
		TST		r0, #T_bit 						; Test if bit 5 is set.
		LDRNEH		r0,[lr,#-2] 						; T_bit set so load halfword (Thumb)
		BICNE		r0,r0,#0xff00 						; and clear top 8 bits of halfword
										; (LDRH clears top 16 bits of word).
		LDREQ		r0,[lr,#-4] 						; T_bit clear so load word (ARM)
		BICEQ		r0,r0,#0xff000000						; and clear top 8 bits of word.
		ADR		r1, switable		 				; Load address of the jump table.
		LDR		pc, [r1,r0,LSL#2]						; Jump to the appropriate routine.
		DCD		do_swi_1
		DCD		do_swi_2
		; Handle the SWI.
		LDMFD		sp!, {r0-r12,pc}^						; Restore the registers and return.
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