9.12. System mode


This section only applies to processors that implement ARM Architectures 4, 4T and later.

The ARM Architecture defines a User mode that has 15 general purpose registers, a pc and a CPSR. In addition to this mode there are five privileged processor modes, each of which have an SPSR and a number of registers that replace some of the 15 User mode general purpose registers.

When a processor exception occurs, the current program counter is copied into the link register for the exception mode, and the CPSR is copied into the SPSR for the exception mode. The CPSR is then altered in an exception-dependent way, and the program counter is set to an exception-defined address to start the exception handler.

The ARM subroutine call instruction (BL) copies the return address into r14 before changing the program counter, so the subroutine return instruction moves r14 to pc (MOV pc,lr).

Together these actions imply that ARM modes that handle exceptions must ensure that they do not cause the same type of exceptions if they call subroutines, because the subroutine return address will be overwritten with the exception return address.

In earlier versions of the ARM architecture, this problem has been solved by either carefully avoiding subroutine calls in exception code, or changing from the privileged mode to user mode. The first solution is often too restrictive, and the second means the task may not have the privileged access it needs to run correctly.

ARM Architecture 4 and later provide a processor mode called system mode, to overcome this problem. System mode is a privileged processor mode that shares the User mode registers. Privileged mode tasks can run in this mode, and exceptions no longer overwrite the link register.


System mode cannot be entered by an exception. The exception handler modify the CPSR to enter System mode. Refer to Reentrant interrupt handlers for an example.

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