9.4. SWI handlers

When the SWI handler is entered, it must establish which SWI is being called. This information is usually stored in bits 0-23 of the instruction itself, as shown in Figure 9.1.

Figure 9.1. ARM SWI instruction

ARM SWI instruction

The top-level SWI handler typically accesses the link register and loads the SWI instruction from memory, and therefore has to be written in assembly language. The individual routines that implement each SWI handler can be written in C if required.

The handler must first load the SWI instruction that caused the exception into a register. At this point, lr_SVC holds the address of the instruction that follows the SWI instruction, so the SWI is loaded into the register (in this case r0) using:

	LDR r0, [lr,#-4]

The handler can then examine the comment field bits, to determine the required operation. The SWI number is extracted by clearing the top eight bits of the opcode:

	BIC r0, r0, #0xff000000

Example 9.5 shows how these instructions can be put together to form a top-level SWI handler.

See Determining the processor state for an example of a handler that deals with both ARM-state and Thumb-state SWI instructions.

Example 9.5. 

	AREA TopLevelSwi, CODE, READONLY								; Name this block 
									; of code.
	EXPORT		SWI_Handler
SWI_Handler
	STMFD		sp!,{r0-r12,lr}					; Store registers.
	LDR		r0,[lr,#-4]					; Calculate address of
								; SWI instruction and
								; load it into r0.
	BIC		r0,r0,#0xff000000					; Mask off top 8 bits of
								; instruction to give SWI number.
	;
	; Use value in r0 to determine which SWI routine to execute.
	; 
	LDMFD		sp!, {r0-r12,pc}^					; Restore registers and return.
	END							; Mark end of this file.
Copyright © 1997, 1998 ARM Limited. All rights reserved.ARM DUI 0040D
Non-Confidential