9.2.1. The processor response to an exception

When an exception is generated, the processor takes the following actions:

  1. Copies the Current Program Status Register (CPSR) into the Saved Program Status Register (SPSR) for the mode in which the exception is to be handled.

    This saves the current mode, interrupt mask, and condition flags.

  2. Changes the appropriate CPSR mode bits in order to:

    • Change to the appropriate mode, and map in the appropriate banked registers for that mode.

    • Disable interrupts. IRQs are disabled when any exception occurs. FIQs are disabled when a FIQ occurs, and on reset.

  3. Sets lr_mode to the return address, as defined in The return address and return instruction.

  4. Sets the program counter to the vector address for the exception. This forces a branch to the appropriate exception handler.

Note

If the application is running on a Thumb-capable processor, the processor response is slightly different. See Handling exceptions on Thumb-capable processors for more details.

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