| Copyright © 1997, 1998 ARM Limited. All rights reserved. | ARM DUI 0040D |
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The type and speed of memory in a simulated system is detailed in a map file. This defines the number of regions of attached memory, and for each region:
the address range to which that region is mapped
the data bus width in bytes
the access time for the memory region.
armsd expects the map file to be in the current working directory
under the name armsd.map.
ADW or ADU accept a map file of any name, provided that it
has the extension .map. See Real-time simulation example: Dhrystone for details of
how to associate a map file into an ADW or ADU session.
To calculate the number of wait states for each possible type of memory access, the ARMulator uses the values supplied in the map file and the clock frequency. See ARMulator configuration for details of how the wait states are calculated.
The format of each line is:
start size name width access read-times write-times
where:
startis the start address of the memory region in hexadecimal,forexample, 80000.
sizeis the size of the memory region in hexadecimal,
for example, 4000.
nameis a single word that you can use to identify the
memory region when memory access statistics are displayed. You can
use any name. To ease readability of the memory access statistics,
give a descriptive name such as SRAM, DRAM,
or EPROM.
widthis the width of the data bus in bytes (that is, 1 for
an 8-bit bus, 2 for a 16-bit bus, or 4 for
a 32-bit bus).
accessdescribes the type of access that may be performed on this region of memory:
rfor read-only.
wfor write-only.
rwfor read-write.
-for no access.
An asterisk (*) may be appended to the
access to describe a Thumb-based system that uses a 32-bit data
bus, but which has a 16-bit latch to latch the upper 16 bits of
data, so that a subsequent 16-bit sequential access can be fetched
directly out of the latch.
read-timesdescribes the nonsequential and sequential read
times in nanoseconds. These should be entered as the nonsequential
read access time followed by / (slash), followed
by the sequential read access time. Omitting the / and
using only one figure indicates that the nonsequential and sequential access
times are the same.
Do not simply enter the times quoted on top of a memory chip. You must add a 20-30ns signal propagation time to them.
write-timesdescribes the nonsequential and sequential write times. The format is identical to that of read times.
The following examples assume a clock speed of 20MHz.
0 80000000 RAM 4 rw 135/85 135/85
This describes a system with a single contiguous section of RAM from 0 to 0x7fffffff with a 32-bit data bus, read-write access, and N and S access times of 135ns and 85ns respectively.
The N-cycle access time is one clock cycle longer than the
S-cycle access time. For a faster system, a smaller N-cycle access
time should be used. For example, for a 33MHz system, the access
times would be defined as 115/85 115/85.
0 80000000 RAM 1 rw 150/100 150/100
This describes a system with the same single contiguous section of memory, but with an 8-bit external data bus and slightly different access times.
The following description file details a typical embedded system with 32KB of on-chip memory, 16-bit ROM and 32KB external DRAM:
00000000 8000 SRAM 4 rw 1/1 1/1
00008000 8000 ROM 2 r 100/100 100/100
00010000 8000 DRAM 2 rw 150/100 150/100
7fff8000 8000 Stack 2 rw 150/100 150/100
There are four regions of memory:
A fast region
from 0 to 0x7fff with a 32-bit data bus.
A slower region from 0x8000 to 0xffff with
a 16-bit data bus. This is labelled ROM and contains the image code,
and is therefore marked as read-only.
A region of RAM from 0x10000 to 0x17fff that
is used for image data.
A region of RAM from 0x7fff8000 to 0x7fffffff that
is used for stack data (the stack pointer is initialized to 0x80000000).
In the final hardware, the two distinct regions of the external DRAM would be combined. This does not make any difference to the accuracy of the simulation.
The SRAM region is given access times of 1ns. In effect, this means that each access takes 1 clock cycle, because ARMulator rounds this up to the nearest clock cycle. However, specifying it as 1ns allows the same map file to be used for a number of simulations with differing clock speeds.
To ensure accurate simulations, take care that all areas of memory likely to be accessed by the image you are simulating are described in the memory map.
To ensure that you have described all areas of memory you think the image should access, you can define a single memory region that covers the entire address range as the last line of the map file.
For example, you could add the following line to the above description:
00000000 80000000 Dummy 4 - 1/1 1/1
You can then detect if any reads or writes are occurring outside
the regions of memory you expect using the print $memory_statistics command.
This can be a very useful debugging tool.
To read the memory statistics use the command:
Print $memory_statistics
The statistics are reported in the following form:
Example 11.1.
address name w acc R(N/S) W(N/S) reads(N/S) writes(N/S) time (ns)
00000000 Dummy 4 - 1/1 1/1 0/0 0/0 0
7FFF8000 Stack 2 rw 150/100 150/100 0/0 0/0 0
00010000 DRAM 2 rw 150/100 150/100 0/0 0/0 0
00008000 ROM 2 r 100/100 100/100 0/0 0/0 0
00000000 SRAM 4 rw 1/1 1/1 0/0 0/0 0
Print $memstats is a shorthand version
of Print $memory_statistics.
You must specify the clock speed of the processor being simulated
in the debugger. In armsd, this is set by the command-line option -clock .
The value is presumed to be in Hz unless MHz is specified.value
In ADW or ADU, the clock speed is set in the Debugger Configuration dialog. To display this dialog:
Select Options ? Configure Debugger... ? Target ? ARMulate ? Configure....
Enter a value and click OK.
See ARMulator configuration for more information.
| Copyright © 1997, 1998 ARM Limited. All rights reserved. | ARM DUI 0040D |
| Non-Confidential | |
| PDF version | |
| Home > Benchmarking, Performance Analysis, and Profiling > Performance benchmarking > Map files |