9.1. Overview

During the normal flow of execution through a program, the program counter increases sequentially through the address space, with branches to nearby labels or branch and links to subroutines.

Processor exceptions occur when this normal flow of execution is diverted, to allow the processor to handle events generated by internal or external sources. Examples of such events are:

It is necessary to preserve the previous processor status when handling such exceptions, so that execution of the program that was running when the exception occurred can resume when the appropriate exception routine has completed.

Table 9.1 shows the seven different types of exception recognized by ARM processors.

Table 9.1. Exception types

ResetOccurs when the processor reset pin is asserted. This exception is only expected to occur for signalling power-up, or for resetting as if the processor has just powered up. A soft reset can be done by branching to the reset vector (0x0000).
Undefined InstructionOccurs if neither the processor, or any attached coprocessor, recognizes the currently executing instruction.
Software Interrupt (SWI)This is a user-defined synchronous interrupt instruction that allows a program running in user mode, for example, to request privileged operations that run in supervisor mode, such as an RTOS function.
Prefetch AbortOccurs when the processor attempts to execute an instruction that has prefetched from an illegal address, that is, an address that the memory management subsystem has determined is inaccessible to the processor in its current mode.
Data AbortOccurs when a data transfer instruction attempts to load or store data at an illegal address.
IRQOccurs when the processor external interrupt request pin is asserted (LOW) and the I bit in the CPSR is clear.
FIQOccurs when the processor external fast interrupt request pin is asserted (LOW) and the F bit in the CPSR is clear.
Copyright © 1997, 1998 ARM Limited. All rights reserved.ARM DUI 0040D