5.2.6. ARM instruction set overview

All ARM instructions are 32 bits long and are stored word-aligned in memory. Instructions are stored word-aligned, so the bottom two bits of addresses are always set to zero in ARM state. These bits are ignored by all ARM instructions that have an address operand, except the Branch Exchange (BX) instruction. The BX instruction uses the bottom bit to determine whether the code being branched to is Thumb code or ARM code. See Chapter 5 Assembler in the ARM Software Development Toolkit Reference Guide for additional information.

ARM instructions can be classified into a number of functional groups:

Branch instructions

These instructions are used to branch backwards to form loops, to branch forward in conditional structures, to branch to subroutines, or to change the processor from ARM state to Thumb state.

Data processing instructions

These instructions operate on the general purpose registers. Generally they perform operations such as addition, subtraction, or bitwise logic on the contents of two registers and place the result in a third register. Long multiply instructions (unavailable in some architectures) give a 64-bit result in two registers.

Status register access instructions

These instructions move the contents of the CPSR or an SPSR to or from a general purpose register.

Single register load and store instructions

These instructions load or store the value of a single register from or to memory. In ARM architecture version 3 these instructions can load or store a 32-bit word or an 8-bit unsigned byte. In ARM architecture version 4 they can also load or store a 16-bit unsigned halfword, or load and sign extend a 16-bit halfword or an 8-bit byte.

Multiple register load and store instructions

These instructions load or store any subset of the general purpose registers from or to memory. Refer to Load and store multiple register instructions for a detailed description of these instructions.

Semaphore instructions

These instructions load and alter a memory semaphore.

Coprocessor instructions

These instructions support a general way to extend the ARM Architecture.

Refer to the ARM Architectural Reference Manual for detailed information on the syntax of the ARM instruction set.

ARM instruction capabilities

The following general points apply to ARM instructions:

Conditional execution

All ARM instructions can be executed conditionally on the value of the ALU status flags in the CPSR. You do not need to use branches to skip conditional instructions, although it may be better to do so when a series of instructions depend on the same condition.

You can specify whether a data processing instruction sets the state of these flags or not. You can use the flags set by one instruction to control execution of other instructions even if there are many instructions in between.

Refer to Conditional execution for a detailed description.

Register access

In ARM state, all instructions can access r0-r14 and most also allow access to r15 (pc). The MRS and MSR instructions can move the contents of the CPSR and SPSRs to a general purpose register, where they can be manipulated by normal data processing operations. Refer to the ARM Architectural Reference Manual for more information.

Access to the inline barrel shifter

The ARM arithmetic logic unit has a 32-bit barrel shifter that is capable of very general shift and rotate operations. The second operand to all ARM data-processing and single register data-transfer instructions can be shifted, before the data-processing or data-transfer is executed, as part of the instruction. This supports, but is not limited to:

  • scaled addressing

  • multiplication by a constant

  • constructing constants.

Refer to the Loading constants into registers for more information on using the barrel-shifter to generate constants.

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