9.11.1. Thumb processor response to an exception

When an exception is generated, the processor takes the following actions:

  1. Copies cpsr into spsr_mode. Switches to ARM state.

  2. Sets the CPSR mode bits.

  3. Stores the return address in lr_mode. See The return address for further details.

  4. Sets the program counter to the vector address for the exception. The switch from Thumb state to ARM state in step 1 ensures that the ARM instruction installed at this vector address (either a branch or a pc-relative load) is correctly fetched, decoded, and executed. This forces a branch to a top level veneer that you must write in ARM code.

Handling the exception

Your top-level veneer routine should save the processor status and any required registers on the stack. You then have two options for writing the exception handler:

  • Write the whole exception handler in ARM code.

  • Perform a BX (branch and exchange) to a Thumb code routine that handles the exception. The routine must return to an ARM code veneer in order to return from the exception, because the Thumb instruction set does not have the instructions required to restore cpsr from spsr.

This second strategy is shown in Figure 9.4. See Chapter 7 Interworking ARM and Thumb for details of how to combine ARM and Thumb code in this way.

Figure 9.4. Handling an exception in Thumb state

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