10.2.2.  RAM at 0x0

RAM is normally faster and wider than ROM. For this reason, it is better for the vector table and FIQ handlers if the memory at 0x0 is RAM.

However, if RAM is located at address 0x0, there is not a valid instruction in the reset vector entry on power-up. Therefore, you need to allow ROM to be located at 0x0 at power-up (so there is a valid reset vector), but to also allow RAM to be located at 0x0 during normal execution. The changeover from the reset to the normal memory map is normally caused by writing to a memory mapped register.

For example, on reset, an aliased copy of ROM is present at 0x0, but RAM is remapped to zero when code writes to the RPS REMAP register. For more information, refer to the ARM Reference Peripheral Specification.

Figure 10.2. Example of a system with RAM at 0x0

Implementing RAM at 0x0

A sample sequence of events for implementing RAM at 0x0 is:

  1. Power on to fetch the RESET vector at 0x00000000 (from the aliased copy of ROM).

  2. Execute the RESET vector:


    LDR PC, =0x0F000004

    which jumps to the real address of the next ROM instruction.

  3. Write to the REMAP register. Set REMAP = 1.

  4. Complete the rest of the initialization code, as described in Initializing the system.

System decoder

ROM can be aliased to address 0x00000000 by the system decoder:


case ADDR(31:24) is
when "0x00"
if REMAP = "0" then
select ROM
else
select SRAM
when "0x0F"
select ROM
when ....

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