12.7.3. Pagetable contents

Finally, the configuration file can contain an outline of the pagetable contents. The module writes out a top-level pagetable (to the address specified for the Translation Table Base Register) whenever ARMulator resets on MMU-based processors.

By default, armul.cnf contains a description of a single region covering the whole of the address space. You can add more regions. A region entry consists of:


{ Region[0]
VirtualBase=0
PhysicalBase=0
Size=4GB
Cacheable=Yes
Bufferable=Yes
Updateable=Yes
Domain=0
AccessPermissions=3
Translate=Yes
}

Region[n]

names the regions, starting with Region[0]. n is an integer.

VirtualBase

is the virtual address of the base of this region. This address should be aligned to a 1MB boundary on an MMU processor.

PhysicalBase

is the address that the base of the region maps to. PhysicalBase defaults to the same as VirtualBase if it is unset. This address should be aligned to a 1MB boundary on an MMU processor.

Size

specifies the size of this region for an MMU. This value is rounded down to the nearest megabyte on an MMU processor.

Cacheable

controls the C bit in the translation table entry.

Bufferable

controls the B bit in the translation table entry.

Updateable

controls the U bit in the translation table entry. (Note that the U bit is only used for the ARM610 processor.)

Domain

specifies the domain field of the table entry.

AccessPermissions

controls the AP field.

Translate

controls whether accesses to this region causes translation faults. Setting Translate=No for a region causes an abort to occur whenever ARMulator reads from or writes to that region.

Pagetable model and protection units

Core models such as the ARM740T and the ARM940T do not have an MMU and pagetables. Instead, they have a Protection Unit and protection regions.

If you use the PageTable model on a core that has a Protection Unit (PU), instead of initializing the MMU and setting up pagetables, the PU is initialized. With the above example, the default set-up initializes the first region (that has the lowest priority) such that the entire memory space (0 to 4GB) is marked as read/write, cacheable and bufferable.

For the 740T, the Protection Unit would be initialized as follows:

  • The M, C and W bits are set in the control register (CP15 register 1), to enable the Protection Unit, the Cache and the Write Buffer.

  • The cacheable register is initialized to 1, marking region 0 as cacheable (CP15 register 2).

  • The bufferable register is initialized to 1, marking region 0 as bufferable (CP15 register 3).

  • The protection register is initialized to 3, marking region 0 as read/write access (CP15 register 5).

  • Finally, the Memory area definition register for region 0 is initialized to 0x3F, marking the size of region 0 as 4GB and as enabled.

For the 940T, the Protection Unit would be initialized as follows:

  • The P, D and I bits are set in the control register (CP15 register 1), to enable the Protection Unit, the data cache and the instruction cache.

  • The cacheable registers are initialized to 1, marking region 0 as cacheable for the I and D caches (CP15 register 2). This is displayed as 0x010, where:

    • the low byte (bits 0..7) represent the dcache cacheable register

    • the high byte (bits 8..15) represent the icache cacheable register.

  • The bufferable register is initialized to 1, marking region 0 as bufferable (CP15 register 3).

  • The Protection registers are initialized to 3, marking region 0 as read/write access for I and D caches (CP15 register 5). This is displayed as 0x00030003, where:

    • the low halfword (bits 0..15) represent the dcache protection register

    • the high halfword (bits 16..31) represent the icache protection register.

    The first register value shown is for region 0, the second for region 1 and so on.

  • The protection region base/size register for region 0 is initialized to 0x3F, marking the size of region 0 as 4GB and as enabled (CP15 Register 6).

  • CP15 Register 7 is a control register. Reading from it is unpredictable. At startup it shows a value of zero.

  • The programming lockdown registers are both initialized to zero. (CP15 Register 9). The first register value shown is for data lockdown control, the second for instruction lockdown control.

  • CP15 Register 15, the Test/Debug register, is initialized to zero. Only bits 2 and 3 have any effect in ARMulator. These control whether the cache replacement algorithm is random or round robin.

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