12.10.4. Configuring the ARMmap memory model

You can configure ARMmap to model several memory managers, by editing its entry in the armul.cnf file:

{ MapFile
;; Options for the mapfile memory model

Counting wait-states

By default, ARMmap is configured to count wait-states in $statistics. This can be disabled by setting CountWaitStates=False in armul.cnf.

Counting AMBA decode cycles

You can configure ARMmap to insert an extra decode cycle for every non-sequential access from the processor. This models the decode cycle seen on AMBA bus systems.You enable this by setting AMBABusCounts=True in armul.cnf.

Merged I-S cycles

All ARM processors, particularly cached processors, can perform a non-sequential access as a pair of idle and sequential cycles, known as merged I-S cycles. By default, ARMmap treats these cycles as a non-sequential access, inserting wait-states on the S-cycle to lengthen it for the non-sequential access.

You can disable this by setting SpotISCycles=False in armul.cnf. However, this is likely to result in exaggerated performance figures, particularly when modeling cached ARM processors.

ARMmap can optimize merged I-S cycles using one of three strategies:


This models a system where the memory manager hardware speculatively decodes all addresses on idle cycles. This gives both the I- and S-cycles time to perform the access, resulting in one less wait state.


This starts the decode when the ARM declares that the next cycle is going to be an S-cycle; that is, half-way through the I-cycle. This can result in one fewer wait-state. (Whether or not there are fewer wait-states depends on the cycle time and the non-sequential access time for that region of memory.)

This is the default setting. You can change this by setting ISTiming=Spec or ISTiming=Late in armul.cnf.


This does not start the decode until the S-cycle.

Copyright © 1997, 1998 ARM Limited. All rights reserved.ARM DUI 0040D