12.16. Events

The ARMulator has a mechanism for broadcasting and handling events. These events consist of an event number and a pair of words. The number identifies the event. The semantics of the words depends on the event.

The core ARMulator generates some example events, defined in armdefs.h. They are divided into three groups:

These events can be logged in the trace file if tracing is enabled, and trace events is turned on. Additional modules can provide new event types that will be handled in the same way.

You can catch events by installing an event upcall (see armul_EventUpcall). You can raise an event by calling ARMul_RaiseEvent() (see ARMul_RaiseEvent).

Refer to Chapter 12 ARMulator in the ARM Software Development Toolkit User Guide for more information and examples.

Table 12.3. Events from ARM processor core

Event nameWord 1Word 2Event number
CoreEvent_UndefinedInstrpc valueinstruction0x2
CoreEvent_SWIpc valueSWI number0x3
CoreEvent_PrefetchAbortpc value-0x4
CoreEvent_DataAbortpc valueaborting address0x5
CoreEvent_AddrExceptnpc valueaborting address0x6
CoreEvent_IRQpc value-0x7
CoreEvent_FIQpc value-0x8
CoreEvent_Breakpointpc valueRDI_PointHandle0x9
CoreEvent_Watchpointpc valueWatch address0xa
CoreEvent_IRQSpottedpc value-0x17
CoreEvent_FIQSpottedpc value-0x18
CoreEvent_ModeChangepc valuenew mode0x19
CoreEvent_Dependencypc valueinterlock register bitmask0x20

Table 12.4. Events from MMU and cache (not on StrongARM-110)

Event nameWord 1Word 2Event number
MMUEvent_DLineFetchmiss addressvictim address0x10001
MMUEvent_ILineFetchmiss addressvictim address0x10002
MMUEvent_WBStallphysical address of writenumber of words in write buffer0x10003
MMUEvent_DTLBWalkmiss addressvictim address0x10004
MMUEvent_ITLBWalkmiss addressvictim address0x10005
MMUEvent_LineWBmiss addressvictim address0x10006
MMUEvent_DCacheStalladdress causing stalladdress fetching0x10007
MMUEvent_ICacheStalladdress causing stalladdress fetching0x10008

Table 12.5. Events from prefetch unit (ARM810 only)

Event nameWord 1Word 2Event number


next pc value




address of branch




next pc value


Copyright © 1997, 1998 ARM Limited. All rights reserved.ARM DUI 0041C