5.5.3. LDFD ARM pseudo-instruction

The LDFD pseudo-instruction loads a floating-point register with a double precision floating-point constant.

Note

You can use LDFD only if your system has a Floating Point Accelerator, or software that emulates one.

This section describes the LDFD pseudo-instruction only. Refer to the ARM FPA10 Data Sheet for information on the LDFD instruction.

Syntax

The syntax of LDFD is:

LDFD{condition} fp-register,=expression

where:

condition

is an optional condition code.

fp-register

is the floating-point register to be loaded.

expression

evaluates to a floating-point constant. The assemblerplaces the constant in a literal pool and generates a program-relative LDFD instruction to read the constant from the literal pool. Two words are used to store the constant in the literal pool.

The offset from pc to the constant must be less than 4KB. You are responsible for ensuring that there is a literal pool within range. See LTORG directive for more information.

Usage

The range for double precision numbers is:

  • Maximum 1.79769313486231571e+308

  • Minimum 2.22507385850720138e–308.

Example

		LDFD		f1,=3.12E106				; loads 3.12E106 into f1
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