E.4. ARM740T processor registers

Table E.3 describes the ARM740T processor registers.

Table E.3. ARM740T processor registers

Register

Description

Access

Data

c0

ID register

Read-only

-

c1

Control register

Read/write

Configuration data

c2

Cache control

Read/write

Cache control flags

c3

Bufferable control

Read/write

Buffer control flags

c5

Memory protection

Read/write

Memory protection data

c6

Memory area definition:

  • Memory Region 0 to 7

Read/write

Base, size, and enable

c7

Cache operations:

  • Invalidate ID Cache

Write-only

SBZ

The encodings to read or write the registers are as follows:

c0 to c3, c5

All data reads and writes occur as expected.

c6

The data that is read or written is a memory area definition, and consists of a base address, a size value, and an enable flag. The memory area is specified by the cp15_current_memory_area variable.

c7

Writing any value invalidates the ID Cache.

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