E.7. ARM926EJ-S processor registers

Table E.11 describes the ARM926EJ-S processor registers.

Table E.11. ARM926EJ-S processor registers

Register

Description

Access

Data

c0

ID register

Read-only

Read-only

Read-only

ID information

Cache configuration

Tightly coupled memory information

c1

Control register

Read/write

Configuration flags

c2

Translation Table Base

Read/write

Translation table base

c3

Domain Access Control

Read/write

Access flags

c5

Fault Status register

Read/write

Status info

c6

Fault Address register

Read/write

Fault address

c7

Cache operations:

  • Invalidate ICache and DCache

  • Invalidate ICache

  • Invalidate I single entry (VA)

  • Invalidate I single entry (set/way)

  • Prefetch ICache Line

  • Invalidate DCache

  • Invalidate D single entry (VA)

  • Invalidate D single entry (set/way)

  • Test and clean DCache

  • Clean D single entry (VA)

  • Clean D single entry (set/way)

  • Test, clean, and invalidate DCache

  • Clean and invalidate D single entry (VA)

  • Clean and invalidate D single entry (set/way)

  • Drain Write Buffer

Write-only

SBZ

SBZ

VA

Set and way

SBZ

SBZ

VA

Set and way

SBZ

VA

Set and way

SBZ

VA

Set and way

SBZ

c8

TLB operations:

  • Invalidate ITLB and DTLB

  • Invalidate ITLB and DTLB single entry (VA)

  • Invalidate ITLB

  • Invalidate ITLB single entry (VA)

  • Invalidate DTLB

  • Invalidate DTLB single entry (VA)

Read/write

SBZ

VA

SBZ

VA

SBZ

VA

c9

Lockdown control:

  • Data Lockdown Control

  • Instruction Lockdown Control

  • Tightly Coupled DMemory Control

  • Tightly Coupled IMemory Control

Read/write

DCtrl value

ICtrl value

DMemory value

IMemory value

c10

TLB lockdown control

Read/write

Base and victim

c13

Process identifiers:

  • FCSE PID

  • Context ID

Read/write

FCSE process ID

ETM context ID

c15

Test and Debug register:

  • Trace Control register

  • Memory Region Remap register

Read/write

Control flags

Remap information

The encodings to read or write the registers are as follows:

c0

A data read with cp15_cache_selected = 0 accesses the ID register.

A data read with cp15_cache_selected = 1 accesses the Cache Configuration register.

A data read with cp15_cache_selected = 2 accesses the Tightly coupled memory information register.

c1, c2, c3

All data reads and writes occur as expected.

c5

A data read with cp15_cache_selected = 0 accesses the Data side FSR.

A data read with cp15_cache_selected = 1 accesses the Instruction side FSR.

c6

All data reads and writes occur as expected.

c7

The function performed is determined by the value of the cp15_cache_selected variable, and by bits [2:0] of the data that is written, as shown in Table E.12.

Table E.12. ARM926EJ-S cp15 register 7 accesses

cp15_cache_selected

Bit 2

Bit 1

Bit 0

Purpose

2

0

0

0

Test, clean, and invalidate DCache

2

0

0

1

Clean and invalidate D single entry (VA)

2

0

1

1

Clean and invalidate D single entry (set/way)

2

1

1

0

Drain Write Buffer

1

0

0

0

Invalidate ICache and DCache

1

0

0

1

Invalidate ICache

1

0

1

0

Invalidate I single entry (VA)

1

0

1

1

Invalidate I single entry (set/way)

1

1

0

0

Prefetch ICache Line

1

1

0

1

Drain Write Buffer

0

0

0

0

Invalidate DCache

0

0

0

1

Invalidate D single entry (VA)

0

0

1

0

Invalidate D single entry (set/way)

0

0

1

1

Test and clean DCache

0

0

1

0

Clean D single entry (VA)

0

0

1

0

Clean D single entry (set/way)

The encoded function uses bits [31:3] of the data that is written, with bits [2:0] cleared.

c8

The function performed is determined by the value of the cp15_cache_selected variable, and by bit 0 of the data that is written, as shown in Table E.13.

Table E.13. ARM926EJ-S cp15 register 8 accesses

cp15_cache_selected

Bit 0

Purpose

2

0

Invalidate ITLB and DTLB

2

1

Invalidate ITLB and DTLB single entry (VA)

1

0

Invalidate ITLB

1

1

Invalidate ITLB single entry (VA)

0

0

Invalidate DTLB

0

1

Invalidate DTLB single entry (VA)

The encoded function uses bits [31:1] of the data that is written, with bit 0 cleared.

c9

A data read or write with cp15_cache_selected = 0 accesses the Data Lockdown control.

A data read with cp15_cache_selected = 1 accesses the Instruction Lockdown control.

A data read or write with cp15_cache_selected = 2 accesses the Tightly Coupled DMemory control.

A data read with cp15_cache_selected = 3 accesses the Tightly Coupled IMemory control.

c10

All data reads and writes occur as expected.

c13

A data read or write with cp15_cache_selected = 0 accesses the FCSE process ID.

A data read with cp15_cache_selected = 1 accesses the ETM context ID.

c15

A data read or write with cp15_cache_selected = 0 accesses the Trace Control register.

A data read with cp15_cache_selected = 1 accesses the Memory Region Remap register.

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