E.5. ARM920T and ARM922T processor registers

Table E.4 describes the ARM920T and ARM922T processor registers.

Table E.4. ARM920T and ARM922T processor registers

Register

Description

Access

Data

c0

ID register

Read-only

Read-only

ID information

Cache configuration[1]

c1

Control register

Read/write

Configuration flags

c2

Translation Table Base

Read/write

Translation table base

c3

Domain Access Control

Read/write

Access flags

c5

Fault Status register

Prefetch Fault Status register

Read/write

Read/write

Status info

Status info[2]

c6

Fault Address register

Read/write

Fault address

c7

Cache operations:

  • Invalidate ICache and DCache

  • Invalidate ICache

  • Invalidate I single entry (VA)

  • Prefetch ICache Line

  • Invalidate DCache

  • Invalidate D single entry (VA)

  • Clean D single entry (VA)

  • Clean and Invalidate D single entry

  • Clean D single entry (index)

  • Clean and Invalidate D single entry (index)

  • Drain Write Buffer

Write-only

SBZ

SBZ

VA

VA

SBZ

VA

VA

VA

Index and segment

Index and segment

SBZ

c8

TLB operations:

  • Invalidate ITLB and DTLB

  • Invalidate ITLB

  • Invalidate ITLB single entry (VA)

  • Invalidate DTLB

  • Invalidate DTLB single entry (VA)

Read/write

SBZ

SBZ

VA

SBZ

VA

c9

Cache lockdown control:

  • Data Lockdown Control

  • Instruction Lockdown Control

Read/write

Base and victim

Base and victim

c10

TLB lockdown control:

  • Data Lockdown Base

  • Instruction Lockdown Base

Read/write

Base and victim

Base and victim

c13

Process ID

Read/write

Process ID

c15

Test and Debug register

Read/write

DCAM and ICAM flags

[1] Revision 1 onwards.

[2] Revision 1 onwards.

The encodings to read or write the registers are as follows:

c0

A data read with cp15_cache_selected = 0 accesses the ID register.

A data read with cp15_cache_selected = 1 accesses the Cache Configuration register.

c1, c2, c3

All data reads and writes occur as expected.

c5

A data read with cp15_cache_selected = 0 accesses the FSR (Data aborts).

A data read with cp15_cache_selected = 1 accesses the PFSR (Prefetch aborts).

Note

The PFSR only exists on revision 1 of the processor onwards.

c6

All data reads and writes occur as expected.

c7

The function performed is determined by the value of the cp15_cache_selected variable, and by bits [2:0] of the data that is written, as shown in Table E.5.

Table E.5. ARM920T and ARM922T cp15 register 7 accesses

cp15_cache_selected

Bit 2

Bit 1

Bit 0

Purpose

1

0

0

0

Invalidate ICache and DCache

1

0

0

1

Invalidate ICache

1

0

1

0

Invalidate I single entry (VA)

1

0

1

1

Prefetch ICache Line

0

0

0

0

Invalidate DCache

0

0

0

1

Invalidate D single entry

0

0

1

0

Clean D single entry (VA)

0

0

1

1

Clean and Invalidate D single entry (VA)

0

1

0

0

Clean D single entry (index)

0

1

0

1

Clean and Invalidate D single entry

0

1

1

0

Drain Write Buffer

The encoded function uses bits [31:3] of the data that is written, with bits [2:0] cleared.

c8

The function performed is determined by the value of the cp15_cache_selected variable, and by bits [1:0] of the data that is written, as shown in Table E.6.

Table E.6. ARM920T and ARM922T cp15 register 8 accesses

cp15_cache_selected

Bit 1

Bit 0

Purpose

100Invalidate ITLB and DTLB
101Invalidate ITLB
110Invalidate ITLB single entry (VA)
000Invalidate DTLB
001Invalidate DTLB single entry (VA)

The encoded function uses bits [31:2] of the data that is written, with bits [1:0] cleared.

c9

A data read or write with cp15_cache_selected = 0 accesses the Data Cache Lockdown Base.

A data read with cp15_cache_selected = 1 accesses the Instruction Cache Lockdown Base.

c10

A data read or write with cp15_cache_selected = 0 accesses the Data TLB Lockdown register.

A data read with cp15_cache_selected = 1 accesses the Instruction TLB Lockdown register.

c13

All data reads and writes occur as expected.

Note

The cp15_current_memory_area variable is not used with the ARM920T processor.

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