E.3. ARM720T processor registers

Table E.2 describes the ARM720T processor registers.

Table E.2. ARM720T processor registers

Register

Description

Access

Data

c0

ID register

Read-only

-

c1

Control register

Read/write

Configuration data

c2

Translation Table Base register

Read/write

Base address

c3

Domain Access Control register

Read/write

Domain value

c5

Fault Status register

Read/write

Fault value

c6

Fault Address register

Read/write

Fault address

c7

Cache operations:

  • Invalidate ID Cache

Write-only

SBZ

c8

TLB operations:

  • Invalidate whole TLB

  • Invalidate Single Entry

Write-only

SBZ

Virtual address

c13

Process ID register (WinCE)

Read/write

Process ID

The encodings to read or write the registers are as follows:

c0 to c3, c5, c6

All data reads and writes occur as expected.

c7

Writing any value invalidates the ID Cache.

c8

Writing 0 invalidates the whole TLB.

Writing an address with bit 0 set to 1 invalidates the TLB entry for that address.

c13

All data reads and writes occur as expected.

Copyright © 1998-2002 ARM Limited. All rights reserved.ARM DUI 0048F
Non-Confidential