Organization

This document is organized into the following chapters and appendices:

Chapter 1 Introduction

Read this chapter for a description of:

  • what is provided in the Multi-ICE product

  • the purpose of the EmbeddedICE® logic within the CPU

  • what has changed between Multi-ICE Version 2.2 and Version 2.1, between Multi-ICE Version 2.1 and Version 2.0, between Version 2.0 and Release 1.4, and between Release 1.4 and Release 1.3.

Chapter 2 Getting Started

Read this chapter for information on how to start working with Multi-ICE. The chapter includes the hardware and software system requirements, how to connect up the hardware, and how to start the Multi-ICE server.

Chapter 3 Using the Multi-ICE Server

This chapter describes how you use the Multi-ICE server, including a more detailed description of configuring the server. There are also sections describing the execution control and user I/O features.

Chapter 4 Debugging with Multi-ICE

This chapter describes how to:

  • connect Multi-ICE to an ARM debugger

  • change the behavior of Multi-ICE using internal variables

  • implement watchpoints and breakpoints and what this means to you

  • access the EmbeddedICE logic directly.

You must read this chapter in conjunction with the debugger user documentation, for example the ADS Debuggers Guide.

Chapter 5 Troubleshooting

Read this chapter for a troubleshooting guide and a list of error messages.

Chapter 6 System Design Guidelines

Read this chapter for information about designing ARM-based ASICs and PCBs that can be debugged using Multi-ICE.

It includes:

  • suggested clocking and reset circuit diagrams

  • how to chain TAP controllers

  • suggested physical connector types and pinouts

  • a description of logic voltage level adaption

  • how power consumption varies with supply voltage.

Appendix A Server Configuration File Syntax

This appendix describes the server configuration file. This file describes a target device group to Multi-ICE.

Appendix B Breakpoint Selection Algorithm

This appendix describes how Multi-ICE allocates your breakpoints and internally generated breakpoints to the hardware. You must read it if you require specific types of breakpoint to be allocated to target memory regions.

Appendix C Command-line Syntax

This appendix describes the command-line syntax of the Multi-ICE server.

Appendix D Processor-specific Information

This appendix describes the differences in the way that Multi-ICE behaves on the ARM10 and XScale microarchitecture processors.

Appendix E CP15 Register Mapping

This appendix contains details relating to register mapping information for the ARM7-based, ARM9-based, ARM10-based, and XScale processors containing a system control coprocessor (CP15).

Appendix F JTAG Interface Connections

This appendix describes and illustrates the JTAG pin connections.

Appendix G User I/O Connections

This appendix describes and illustrates the additional input and output connections provided in Multi-ICE.

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