D.1.1. Limitations of the ARM1020T (Rev 0) processor

Multi-ICE does not support the following facilities when connected to an ARM1020T (Rev 0) processor:

The processor does not implement writing to memory in debug state when the cache is switched on correctly. This affects several debugger actions, including downloading code and setting software breakpoints. You must therefore obey the following rules:

If the DCache is switched on when the processor enters debug state, Multi-ICE must clean the DCache. To do this it downloads some code to memory at the configured cache clean code address and runs it. Because the processor does not correctly implement writing memory in debug state when the cache is switched on, Multi-ICE might not be able to download this code. To ensure that it can, you must:

You can do this by either:

Copyright © 1998-2002 ARM Limited. All rights reserved.ARM DUI 0048F