D.2.1. Behavior on system reset

The XScale processor debug architecture differs significantly from that of other processors based on the ARM architecture. It enters debug state, for example when a breakpoint is hit, by branching to a debugger-specific handler in a new processor mode called Debug. This handler is stored in a special part of the processor instruction cache, and is usually put there when the processor is held in reset.

Multi-ICE is limited to the following ways that it can connect to an XScale microarchitecture processor:

Note

Multi-ICE Version 2.0 only supports connection using a reset.

If you want to reset the processor to connect to it:

If you intend to reconnect to a previously set up debug handler installed either through the use of hot-debug enabled system firmware or from a previous Multi-ICE session:

Use the Processor Settings tab on the Multi-ICE configuration dialog to configure the debug handler address in the special cache that is used (see Processor Settings Tab).

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